Solutions for Enabling a Data-Driven World- Tom Beckley Keynote @ CDNLive EMEA 2019

So I've been here five years in a row, but last year I had to do an IEEE presentation and was unable to come. But it's great to be back. The reason I love to come to Europe is to me, Munich is the mixed-signal and system capital of the world. My products are customized SoCs, packaging, board, systems analysis, simulation, verification. It's ideal for the profile of companies here in Europe. So it's my pleasure to be back here with you. We are going through interesting times, like we talked about at dinner last night. With the advent of sensors, lots of data coming in, AI, and the cloud, no one doubts anymore the transformative potential of big data. As big data plays out, it will upend entire industries. Companies are asking themselves, what does it mean for me to survive and thrive in a world where data is important and data analytics could be the difference between survival and being highly profitable? There's little doubt that data is streaming in across platforms from sensors, AR/VR, more than a billion plus phones in use now across the globe. Tremendous amounts of data are coming in. This data is being coupled with data centers across the globe. Thousands and thousands of miles of fiber optic cable is being laid to move that data to appropriate places, and the data centers are building specialized compute capabilities to handle that. This is a result of high bandwidth, low cost memory, specialized compute power, high bandwidth transmission, and low latency. Put all four of those together, and we're at this inflection point. Data is becoming the new corporate asset. All of a sudden, there's so much compute power available for computer scientists that at the center of all this activity now is AI. With AI, increasingly complex and sophisticated algorithms are being developed. We'll talk a little bit more about that. From video to gaming to IoT to automotive, data is growing at a CAGR in excess of 70%. Because data is becoming the new corporate asset, companies are digitizing their entire experience with consumers, from when you first start to search for a product all the way through to when you end using that product. Everything is being captured. That is shaping product development, marketing strategies, business strategies. At the same time, everything on the shop floor is being digitized to improve operational excellence and productivity. This is a huge systems opportunity. It's a huge opportunity for Europe. This will take the form of new SoCs, stacked die and systems, and package modules, chipsets, miniaturized boards, electromechanical systems with a vast software stack. It's a huge opportunity. We've seen a lot of waves in semiconductor computing over the years: Intel and microprocessors, Qualcomm and mobile gaming, Nvidia. The next major wave is going to be AI. Nvidia is in an interesting position with their GPU architecture. It works on a lot of algorithms reasonably well, but it's not optimized. The power footprint is way too high relative to what is needed. Therefore, there are a number of new startups unfolding. In addition to those new startups, all of the large cloud players and a lot of big systems companies are investing heavily: Amazon, Google, Facebook, Huawei. At the Consumer Electronics Show in January of this year, Huawei showed a new AI chip, the company 920 I think it's called, 20 billion transistors, 7 nanometer, based on the ARM v8 architecture. Think about that, dedicated to AI processing. While the semi industry is going to see great growth over the next eight to ten years, the AI segment will grow at three times that rate. Everybody's wondering, what does it mean for my company and what does it mean in terms of opportunity? As 5G matures, this will actually accelerate big data and AI. 5G won't be four times faster than 4G, it will be 40 times faster than 4G with much higher bandwidth. It will be the foundation for the driverless car, smart city, automation on the factory floor with IoT. But it will require a lot of interesting technologies. A lot of things have to be miniaturized, and it is a combination of RF, millimeter wave, and microwave that has to be unified and working together. So it'll mean analog, RF, everything including optical in a package, lots of MIMO antennas with very small footprints scattered all over the place. Pilot programs are underway. In fact, there's one with Verizon right now in Chicago. It hasn't gone very well. Most of the pilot programs right now are struggling to get all of the infrastructure in place for 5G to really work well. And then of course you need 5G enablement on your phone. But give it time, and in a few years we'll wonder how we did without it. Another dynamic that's changing our lives that we should take into account: we all know Moore's Law. It has been the perfect storm for electronics. I know everyone in this room thinks that it's your hard work and your brain power that has made you so successful. It's easier to be successful if you're riding on top of a tidal wave, and that's what this has been. Think about it: every time we push to a new node, we double the number of transistors every 18 to 24 months. Does that mean smaller footprint, lower power, higher performance, lower cost? That's been the rule now for decades upon decades. The rule is changing. While it's still in place somewhat for big digital, maybe memory, maybe processors at advanced FinFET nodes, just like that 7 nanometer AI chip from Huawei, it's getting very expensive. We know as device physicists, maybe 3 nanometers, maybe 2 nanometers, design starting right now at 5. So we're getting close. The physics challenges will overwhelm the scalability of CMOS. On the left-hand side of this chart, you see the world of more than Moore: the physical world, analog, RF, photonics, MEMS, sensors. They have never scaled like digital scaled. What we'll see in the future in the world of more than Moore is optimized physical with high bandwidth memory and high bandwidth and high performance processing power in a packaged wafer level stacking modules and more. For the design, analysis, and verification of these complex systems, Cadence has something that we call System Design Enablement. We're taking this to the next level. We just announced this about a month ago. We're calling it Intelligent System Design. At the base are our core platforms for EDA and for IP. But we're not stopping there. For the world of more than Moore, we're creating 3D solutions with 3D analysis capabilities that enable this world to unfold and to be productive. We're layering in, we're taking advantage of big data, and we're layering in machine learning algorithms. I'll talk more about this throughout all of these platforms so you can be more productive and take advantage of these trends that are unfolding. We have design platforms. I think you're pretty familiar with them. I of course have the custom IC, IC package, PCB design and analysis platforms. About 1,250 engineers in my team alone, just to give you a flavor for it. About 5,000 people in R&D at Cadence. It's a big group. If you want to design an SoC, you use Virtuoso, Innovus. You want to do package or board design, you have Cadence Allegro system and package, Advanced Package Designer. If you want to do hardware-software co-design, emulation, acceleration, we have great platforms with Palladium and Protium with a lot of software that goes with that. Verification and simulation software like Spectre and Xcelium and Jasper, vManager, vPlanner. Analysis tools like Sigrity, like Clarity, PSpice, and more. All of this is used to build our IP, and we have bleeding-edge IP now at 7 nanometer, and we're working on 5 nanometer. Cadence also has the richest and largest portfolio and offering for doing semiconductor and systems design on the cloud. Whether you want to manage your own on-prem/cloud world or whether you would like Cadence to help you manage it, we have a number of offerings in the hosted area, in the Cadence managed area. We have hosted design solutions. We have Palladium on the cloud for hardware-software co-design and acceleration. Our latest offering, just announced a month ago, is the CloudBurst platform. It's the easiest way, the most flexible way to use Cadence's solutions on the cloud. It's all web browser-based, and we've designed it and we're working with key partners like AWS, like foundry partners like TSMC. In fact, I think two months ago, Barefoot Networks taped out a 500 million instance IC. They did timing signoff with Tempus on the cloud using CloudBurst. So it's up and running. There is a booth in the back. There are going to be some sessions today. I encourage you to stop by. I think some of our cloud partners like AWS will talk about how they're optimizing the cloud for semiconductor and electronic systems design and enhancing security of the data. Speaking of security of the data, we're entering into a world, we had this discussion at dinner last night, of hyper-connected systems. In the vehicle itself, multiple vendors, lots and lots of challenges come with that. Few things are more important than embedded safety and security. That's why at the beginning of this year, Cadence announced a partnership with Green Hills Software and an investment that Cadence has made in Green Hills Software because of the strategic importance of this type of technology integrated and starting at the system level design aspect. Green Hills is the leader in secure RTOS. They have a rich and powerful software development platform. This is not something you do as an aside. While you plan your system, while you plan your chip, you should bring in Green Hills early. They have a booth here. We're working with them to integrate our hardware and software verification solutions. Please stop by, please meet them, and take the opportunity to better understand how you're going to ensure your products are secure in this world that's unfolding. I talked about Cadence solutions already. I want to go into detail on them, but I want to highlight the fact that we're going to take all of these design platforms and we're going to take them into a 3D more than Moore world. Of course today you can do mixed-signal design on OpenAccess with Virtuoso and Innovus. You can use AMS Designer to do co-simulation of Spectre and Xcelium on digital and analog. You can move it into the world of automotive and functional safety. You can do ISO 26262 compliance because we have a dVerifier for analog verification now integrated with vManager for digital verification. So you have mixed-signal verification that you can document and comply with. We're developing new tools, and I'll talk a little bit about that, and new solutions for the world of more than Moore. The first I'd like to comment on is the Virtuoso RF Solution. About a year ago at the International Microwave Symposium in Philadelphia, we announced the Virtuoso RF Solution. Again, this is not done in a vacuum. It's not all Cadence technology. Just like I talked about partnering with Green Hills, partnering with cloud providers and key foundries, in this case we partnered with a leader in 5G and test measurement, National Instruments. With National Instruments, we got access to all the 3-5 models, all the models for millimeter wave design. So now you can co-design not only CMOS but gallium nitride, gallium arsenide, SiGe as part of an RF solution and a millimeter wave solution. You can design not only the chip but the package and the module in Virtuoso, or you can import it from our system and package Allegro or Advanced Package Designer tool suite. This includes integrated 2.5D planar level electromagnetics that is also from National Instruments, it's the Axiem solver, or Cadence's 3D electromagnetic solver, both integrated into the design platform. While you're designing, analyzing, verifying, your golden schematic is maintained. We also introduced the Virtuoso Photonic Solution. Of course photonics is key for the world of data centers, networking, and automotive. In fact, I live in Pittsburgh, Pennsylvania. I had a spin-out from Carnegie Mellon University that Sanjay talked about, Neolinear, was acquired in 2004. Uber has a very large site in Pittsburgh. They have about 80 test vehicles on the road. They use a combination of camera technologies, radar technologies, and lidar technologies. A good friend of mine runs that software development group. He talks about the need to get 25 gigabits of data in and out of that vehicle per hour. That's photonics in the cloud, that's photonics in the vehicle itself with tremendous amounts of storage and edge processing at the inference. Today, actually three years ago, they started their test vehicles. All of them had a very large mechanical unit on the top, the lidar unit cost almost as much as the vehicle itself, with rotating mechanical beacons on it, collecting all of that data. I've seen the latest ones, they're Volvo cars that they use. It is probably one-fifth the size of what it was, and this is just in three years. It's going solid-state, using a flow just like you see here. So now inside of Virtuoso, I can co-design of course the mixed-signal technology using Cadence's offerings, but I can also co-design the electronics and the photonics with our partner Luceda with their photonics simulator. I can co-design the electronics and the MEMS. I can design the chip, the package, the board, the entire system. I can do analysis for signal and power integrity, thermal, electromagnetics. I can even do the analog beamforming inside of Virtuoso because we have a partnership with MathWorks. With MathWorks, we've integrated MATLAB into the analog design environment, so I can pull in the Phased Array System Toolbox from MATLAB and do the analog beamforming. These are the types of more than Moore solutions that we're taking into our platforms. We're used to a world of more Moore where everything gets smaller and everything becomes more powerful and lower cost. But now we're moving, because of what's happening to Moore's Law, into this world of more than Moore. But don't kid yourself, in the world of more than Moore, everything needs to stay miniaturized, the footprint needs to stay small. That's why TSMC is investing billions and billions of dollars each year in advanced packaging for 3D IC, for wafer level stacking, optimizing certain components at larger nodes, maybe like power semis, and other components like digital memory at much smaller nodes. Because of this, about a year and a half ago at Cadence, we recognized the need to look at miniaturization and what it has in terms of heterogeneous system design and the physics effects. Whenever we squeeze things down, we have to worry about reliability, we have to worry about thermal, we have to worry about electromagnetics, we have to worry about structural. Therefore, we formed a group about a year and a half ago. We took the power management group out of the digital side of the equation, we took the power and signal integrity group out of the package and board group, and we combined them into one team. That team is now looking at everything multiphysics. It's now about 250 people strong, it's one of my groups. We didn't stop there. We layered in almost $10 million in incremental funding. Just last month, we introduced our first new product. It's called the Clarity 3D Electromagnetic Solver. I want to give you a little feel for this. This was introduced at CDNLive San Jose just a month ago. This was completely re-architected from scratch, keeping the cloud in mind. Everything is architected to be run on the cloud with massive parallelism. Because of the way it's been implemented, we have effectively unprecedented performance and capacity with golden accuracy. Beyond that, it's integrated into the design platforms. You don't want to wait till final signoff to find you have a problem with electromagnetics. You'd rather understand that as you're doing design. So it's integrated in Virtuoso, Allegro, and Innovus. I mentioned before that I had a technology company out of Carnegie Mellon University. I went to Carnegie Mellon from Avanti back in the mid-90s, and we spun out this company looking at analog IC design automation for both place and route and for synthesis, circuit synthesis. But at about the same time, maybe two years before us, there was a second spin-out from Carnegie Mellon University that became pretty famous, a company called Ansoft. Ansoft had a very famous tool called HFSS. It's still used today, it's a great tool. Of course, Ansoft got acquired by Ansys, and things have unfolded. I know the professor who did a lot of work in this area, and I understand the architecture of what they have. It's a great product, but it is now a couple of decades old. It wasn't architected for the cloud, it wasn't architected for big data, it wasn't architected for small footprint machines parallelized. That's what we have done with Clarity. The conventional approach today, let's take the example of maybe a high-speed SerDes, maybe 112 gig, 7 nanometer SerDes. Cadence has a great one by the way. This is driving the entire data center world, these types of products and IP. What happens? The chip, the signal goes across the chip, it goes through a package, goes through a board, goes into a backplane, goes through cables and connectors, makes its way to another chip packaged on a board. All of that has to be modeled accurately and quickly and efficiently. Today, every place you have to break that into multiple structures, you analyze the individual pieces, and then you stitch them back together. It takes a long time, it takes a high memory footprint, it's error-prone. With Clarity, we've overcome that. We use the power of the cloud, we use massive parallelism, not just the sparse matrix solver, those physics have been around for a long time, but also the adaptive meshing. It effectively gives us basically unbounded scalability. So you don't need to break structures into pieces, you can analyze the entirety. Early results from customers are very encouraging. On the left-hand side, we see the world of high data rates, DDR4 with a package and a board and connectors, more than 7x performance improvement, no need to break up the structure. In the middle, we see a data center application, high-speed SerDes probably like we talked about, in this case the high-speed connector at a 10x performance improvement. On the right, the world of more than Moore with wafer level package on package, 12x performance improvement. The larger the circuit, the higher the performance improvement. Note the footprint: in the middle, 8 gigabyte average memory versus conventionally used today 256, and on the right 41 gig versus 500. So it's a much more cost-effective ROI on the capital equipment side of the equation, whether it's your computer resources or a hybrid approach with the cloud. That's why Katherine Shaw, I've known her for a long time, she runs one of the largest design teams at HiSilicon. HiSilicon is the captive subsidiary of Huawei, and they work, as you can see by the type of chip that's shown there, they work on the mobile communications chips that are being used in their very successful phones. She states that legacy 3D solver technology has been incapable of meeting our needs for simulating the entire system: the chip, the package, the board, and the enclosure. That's why she's excited about Clarity. Let's step back and think about this in the world of a system of systems and the importance of it as more than Moore unfolds. We know that spatial recognition is key to the autonomous vehicle, it's key to robotics, whether it's in the home or on the shop floor. Here we see a camera module, an advanced camera module that's being developed. Of course it's split into multiple pieces. The first part is the optical lens, and with that is a board with the CMOS image sensor and related electronics. Then you have the main board next to it, that of course is going to have things like DDR4, Ethernet cable out, and the like. And then that's all enclosed in a very small mechanical housing. The mechanical housing is also done through partnerships, new partnerships in our ecosystem with Cadence. You might be using SolidWorks or maybe CATIA from Dassault or maybe PTC to form a complete system. The rigid flex boards, these miniature boards, are designed in Allegro, and then they're stacked on top of one another with a flexible connector, and then they go into this very small housing. I don't need to tell you as electrical engineers what happens with electronics in small housing. We have to worry about thermal. We know as temperature goes up, leakage goes up, resistance goes up, and we have to worry about reliability as a result of that. On the top right-hand side of this chart, we see that we can do an analysis using the Sigrity PowerDC technology of current density versus temperature. As we go to that main board and we have high data rates, then I'm worried about eye openings and signal integrity, EMI. So I can use a combination of Sigrity PowerDC and Sigrity PowerSI to make that analysis. But let's now assume that we're in a vehicle of the future and that this miniaturized camera unit is going to sit near the rear-view mirror on the windshield of that car. What happens in the summertime as the sun beats on it year after year after year? How do you know that new equipment in the world of more than Moore, how do you know it's going to last the life of the vehicle, 10 years, 15 years, maybe longer? So you have to be very proactive on how you engineer it. You might say to yourself, I think what I'm going to do is that CMOS image sensor, it's got a ton of data converters all around the periphery of it, I'm going to have to get the heat off of that, or maybe the DDR4, and so I'll put a heatsink on it. But wait, you've got RF circuitry in that vehicle, it's a system of systems. How do you know you're not impacting the RF circuitry? So you might say, well I'll just drill some holes in the mechanical housing and the chassis itself to alleviate the heat, but you'll change the electromagnetic profile of that system and nearby systems when you do it. These are the types of multiphysics problems we're looking at by creating these new massively parallelized next-generation physics analysis tools to be used in design, not just final signoff, but to be used in design. There will be more coming. Everything will have the same approach, so stay tuned for that. I want to spend a minute and talk about AI and machine learning. We're doing a tremendous amount at Cadence in this area. Some of it is externally funded, much of it is internally funded. I put it in three major categories. There's enablement: we can provide IP that can help in developing those next-generation data center chips that are needed for AI. We have our core EDA platforms, and we're using machine learning algorithms to improve smarter simulation, improve floor planning, better power, performance, area. I'll show you an example of that. You might be surprised to learn that for six years now, we've been using machine learning in Virtuoso as part of our electrically aware design technology. It's in the background, you don't even know what's going on. We're even doing fundamental research at Cadence, first I've seen in my 15 years since I joined the company in 2004, really fundamental research. If you take my team as an example, I have the custom IC, IC package, PCB team. Last year in July, we received, just my team alone, a $25 million grant from the US government from DARPA, the Defense Advanced Research Projects Agency. DARPA's target for this is push-button analog design, push-button package design, and push-button board design. I don't want people to get depressed. I don't want you to think that you have to become an Uber driver for your next career. This is what's called a moonshot program. If you think about 2003, there was the first race in the desert in Nevada where universities and companies and DARPA funding launched the first autonomous vehicles. We're now at 2019, we have an autonomous vehicle yet, right? This is a long journey. But along the way, look at the massive amounts of evolutionary technology and some revolutionary technology that has unfolded. This is the kind of research we're doing, and we're doing it not in a vacuum. For instance, in my group, we have three WeWork sites. We have a WeWork site going in Cambridge, Massachusetts, right in Boston, right next to MIT and Harvard. It just happens to be there for a reason. We have another in Pittsburgh with Carnegie Mellon University, and a third in Silicon Valley near UC Berkeley and Stanford. So we're pulling the best and the brightest. We have about 40 PhDs working on this internally on this program right now. More on that in just a minute. Let's talk about a couple of these other areas first. Late last year, Cadence introduced the Tensilica DNA 100 processor. This is ideal for AI and machine learning for edge inferencing. It's a sparse compute engine with high MAC utilization, 0.5 tera MAC per processor, but you can get to hundreds of tera MACs by stacking them. The beauty of it, and I don't know how much you know about machine learning and sparse neural networks and the like, but it takes advantage of the inherent sparsity in neural networks. That's really powerful. This is extremely popular IP. All those startups, all those big system companies are moving in this direction. So there's an example of enablement. My colleague Tinchy, he runs the digital and signoff team, and he's got some interesting work going on in machine learning algorithms across his digital flow, in digital synthesis with Genus, in place and route with Innovus, and in timing signoff with Tempus. He's looking to minimize across the flow total negative slack, and the results are pretty stunning. Of course that's improving power, performance, area. The beauty of these types of implementations is that they're behind the scenes, just like Virtuoso I talked about. The user doesn't even see them, they just get better results faster. So expect a lot to unfold on that front. Today, I'm pleased to actually announce yet another major breakthrough by Cadence. This is actually in Paul Cunningham's team, another colleague of mine. He runs the system verification group with all the hardware and digital verification tools. This is the third generation JasperGold platform. This includes a lot of machine learning technology. For instance, it's called Smart Proof technology. I don't know how much you know about the world of Jasper and Boolean expressions and how you use mathematical proofs, but we use machine learning. This was based on literally hundreds and hundreds of designs and so much training data. These machine learning algorithms were developed for SAT, or satisfiability, Boolean solver inference. So things are faster out of the box, but for recurrent regression runs, they are much faster. In fact, ST found 2x improvement out of the box, 5x for regression runs, and convergence, proof convergence, was significantly enhanced. What a combination. The team didn't stop there. They then doubled the design capacity for larger SoCs, and they decreased the memory footprint by 50%. For things like stimuli and checker coverage, it's much easier to build those into the proof statements. All of that is the third generation now with machine learning. You'll see this happen across tools and solutions from Cadence. I mentioned that DARPA program. It was $25 million funded over four years. I called it a moonshot program. We're ten months into that four-year program. It's based on something that the US government calls the Electronic Resurgence Initiative, the ERI program. If you look it up, you'll see lots and lots of it's all about more than Moore. It has three major pillars. The first one is new architectures. The second one is new materials, because CMOS will exhaust itself. And then the third one is new design tools and new design methodologies. We're in that third pillar where my group received that $25 million funding. I talked about the university work that we have going on. We're also doing a lot of work with leading commercial companies. Of course there are some in the defense ecosystem like Northrop Grumman, Lockheed Martin, and others that we're working with. Nvidia is a formal partner in the program. We're very interested in some of their architectures and how we can use that. We're doing a lot of work with Intel. I wanted to show you here some early results. These were published late last year. This was machine learning algorithm development we did inside in that Cambridge WeWork site that I talked about. It looks at very sophisticated processor interposer routing and the placement. The via placement is really critical to make that successful. On the left, it was a little difficult to see, it takes Intel every time they do a variant about 128 hours of manual routing. With the machine learning approach we did, in 30 minutes. Now it's machine learning, so this was November of last year. We've run more designs through it. Same design now takes about five minutes to run through. That's the world of machine learning that's unfolding, folks. That's the world of big data that's unfolding. That's why some of these things will be evolutionary, some might be revolutionary as they unfold. To conclude, whether you're a semiconductor company or a semiconductor company that's becoming a system semi, which most are, or you're a system company, you should be worried about, you should be interested in how you utilize data and data analytics and what the world of more than Moore means to you and how you assess these dynamics as you look five years down the road and ten years down the road. I can tell you one of the reasons Cadence is doing so well is we really have the best collection of tools. Whether you're designing at the IP level, the chip, the package, the board, or the system, we have solutions. We'll continue to invest in progress to help me help you navigate the world of more than Moore and to make your business successful. Thank you so much.