Senior Vice President of IP Group, Synopsys
IP Powering Chip Designs – Cars to Cloud - John Koeter, Sr. VP, Marketing and Strategy, Synopsys
From automotive to the cloud, high-performance systems are requiring new architectures to optimize data processing, networking, ...
About John Koeter
John Koeter, Senior Vice President of the IP Group at Synopsys, has been discussing the company's role in advancing RISC-V-based system-on-chip (SoC) innovation. In a September 2024 keynote, he announced a new family within Synopsys's ARC product line called "Cleverly ARC5," which includes three product families targeting deeply embedded 32-bit processors, real-time applications with hardware virtualization, and a full 64-bit multicore host processor supporting Linux. Koeter stated that Synopsys is committed to supporting the RISC-V ecosystem with a broad portfolio of IP, including interface IP, security processors, and safety-certified tools. He cited projections from Semico that automotive RISC-V-based processors will be valued at nearly one billion dollars by 2027, and noted that 30% of IoT devices are expected to be based on RISC-V by 2028. In a 2021 presentation, Koeter addressed trends in semiconductor design driven by shifts to public cloud computing and automotive zonal architectures. He said that according to Gartner Dataquest, about 90% of applications are currently run on on-prem clouds, but that is expected to flip to nearly 80% on public cloud within four to five years. Koeter described the current period as a "golden age of semiconductors," with high innovation levels driven by AI accelerators, graphics chips, and server chips. He highlighted Synopsys's investments in die-to-die interfaces, high-speed IP for data centers, and automotive-grade IP certified for standards like ISO 26262, and noted partnerships with Infineon, Qualcomm, and Bay Robotics.
Transcript (12 segments)
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John Koeter0:03
Hello, my name is John Koeter. I'm the Senior Vice President of Strategy and Marketing for the Solutions Group at Synopsis. Welcome. It's a pleasure to virtually talk to all of you. I miss so much coming to Israel and into Europe. I visited there many times a year typically before the whole pandemic hit and I look forward to doing it again. Today I'm going to be talking about how IP is powering the next generation of chip designs from cloud to the car. First, let me talk about some of the major changes that we are seeing right now. In the data center there is a gigantic shift that happened by the pandemic. Today, at least according to Gartner Dataquest, about 90% of the applications are being run on on-prem clouds and over the next four to five years we expect that to really flip and have almost 80% of the applications being run on the public cloud. That is driving a gigantic shift across the entire semiconductor industry and creating amazing opportunities for all of us who work in the semiconductor industry. I'm going to talk about just a few of those in the next couple of slides. But before I do that, I'm going to talk about how the data center is really driving new design starts and innovation. We're really in kind of an almost golden age of semiconductors right now. The innovation levels are just so high, driven by that dynamic that we just talked about. Whether it's AI accelerators or graphics chips or next generation server chips or smart NICs, you name it, there's so much innovation happening right now and it's creating a great opportunity for all of us.
As we can see from this IBS global semiconductor report right now, if you look we're right here in the area of 2020-21, about $80 billion worth of opportunity for semiconductor and that's expected to roughly double over the next five or six years with a compounded annual growth rate of more than 10%. We're also seeing that there's a rapid evolution of processes to go along with that. Today, many of these data center chips are in 7 nanometer. We're also very, very rapidly seeing them move to 5 nanometer and 3 nanometer. In fact, numerous foundries really are saying that high performance compute or cloud compute is really going to be the driver for their next generation of processes.
One of the things that I also wanted to talk about is the explosive growth in artificial intelligence. We all know that artificial intelligence is here and it's really revolutionizing every aspect of the semiconductor design process. One of the root causes of that, being driven by AI chips, is that you're going to need to move an incredible amount of memory on and off the chip and you need different types of memory compute. This is driving a tremendous shift in the way our customers architect the design. It's also driving a tremendous shift in the way people think about storage. You can see on the graph here just a massive growth in compute and memory needs that are driven by these very, very complex AI algorithms.
One of the things that is growing because of this is enterprise level storage, which is growing at almost 18%, 17.8% to be exact, from 2019 through 2024. SSDs are rapidly transitioning into different new semiconductor processes as well to keep up with this tremendous demand. Today, many enterprise SSDs are in like a 16 or 12 nanometer node, but that's rapidly shifting to 7 and 5, and we see an adoption of 3 nanometer as well in terms of the designs being driven very aggressively by these enterprise storage applications. Persistent memory is a new really important trend here and that's being widely adopted for low latency storage and large memory applications to augment DDR. SSDs being driven by the need to handle all of this data are moving from PCIe to PCIe 5.0 and in some cases even PCIe 6.0 to handle the system interface and to handle all the data coming on and off the chip here. Compute storage is fundamentally changing and arrays are going to be handling more and more of the compute data storage as we move forward. So just a tremendous amount of change happening in every aspect of the data center, being driven by, among many other things, artificial intelligence and the increased usages that we talked about.
Now specifically I wanted to double click into one more area of memory, on-chip memory interfaces externally driving external DRAMs. There are many different options that our designers have. You can have DDR5, which has by far the biggest capacity. You can have LPDDR5 or rapidly evolving now into LPDDR5X, which has excellent low power characteristics and is popular in applications such as high-end mobile as well as in automotive. You have GDDR6, which is a contender in terms of a trade-off between bandwidth and latency and the fact that it doesn't require any kind of interposer design. And if you're just looking at flat out raw highest performance, highest bandwidth in things like an AI training engine, that's where HBM3 really shines. No other memory technology delivers the same kind of total bandwidth as HBM3 does. Of course it does require complex packaging, and that's another major trend happening in the semiconductor industry right now. As many people in the supply chain are looking to reduce the cost of these 2.5D or 3D packages, we're seeing an absolute explosion of innovation in the packaging area. At Synopsis we're really focused on DDR5 because of the capacity in things like a server chip, LPDDR5X for mobile and automotive applications, and HBM3 for the raw bandwidth.
Now I wanted to also talk about a brand new trend in semiconductor: the system in package, or SiP. Really it's the new SoC. Today chips are getting very large and very complex and they're hitting the reticle limits in some cases. These chips are being split into multiple chips; we call that a homogeneous use case. Think about something like a big Ethernet switch chip or something like that which is being split into multiple chips. In that case, what you want the die to die interconnect to be is essentially like an extension of your internal bus. You want it to be very fast, very low latency, very error free. That's driving one class of die to die connectivity solutions that we offer here at Synopsis. But there are other use cases, what we call disaggregation use cases. What used to be a monolithic server chip that had the CPUs on it and all the I/O chips is now being disaggregated into multiple chips. You might have the main server chip that's continuing to race to 5 nanometer to 3 nanometer, and then you may see the I/O chips being put on a separate chip at, say, 12 nanometer or 7 nanometer technology. This system in package, or SiP, is really driving significant changes to the way the basic architectures are being designed. One key to making SiP work is to have very high speed, very low power, very low latency, error-free die-to-die interfaces. That's one of the things we're investing in very heavily here at Synopsis, whether it's a parallel interface or a serial die to die interface.
Now I just wanted to come back and summarize all of the IP that we have for high performance compute, driven by all these trends in the market that I just talked about. We have very high speed SerDes up to 112 gig and long reach capabilities here, for things like top of rack applications. For memory interfaces we have DDR5 being used in things like server where it's all about capacity, or LPDDR5 or 5X where it's all about low power, or HBM3 where it's all about bandwidth. We also have global memory structures here that we optimize specifically for high performance compute. We have SRAMs, we have multi-port memories again which are very important in things like networking applications. I talked about how we have both serial and parallel die to die interfaces as well. And then of course we have the system interface, the CXL PCIe 5 going to PCIe 6 along with CXL, which is used for many other things including cache coherency. We're really seeing a lot of increase in demand for CXL. One thing that was brand new that we just introduced was security modules for PCI Express and CXL to really secure that system interface into the chip. So we have a very robust performance portfolio of IP here for high performance compute.
Now I'm going to switch over to the car, where just as significant a number of trends are happening right now. In years past there might have been 30 to even 100 ECUs in a car. Then those ECUs started to consolidate into controllers like the comfort domain controller, the powertrain controller, the ADAS controller, the infotainment controller, or the connectivity controller. That's today's state of the art design: you have these big chips that are being switched through a gateway and they really consolidated all of those individual ECUs we talked about in yesterday's car. But where we really see the automotive industry moving is into these new zonal architectures. You have a zonal gateway and then you funnel all of the data coming in into a central processing module. That's really fundamentally changing how we go about architecting the chips and the demand for those chips. In terms of processes, today it's very common for high-end automotive chips to be in a 16 or 12 nanometer type of process. That's rapidly moving to 7, 5, and even 3, driven by the centralized processing modules which are further consolidating the ECUs.
When it comes to automotive, we all know we're on the path to self-driving cars. It's going to be a long path; it's not going to happen tomorrow. But one of the things that's really important here when we did a survey of what is one of the most important factors when you're developing automotive chips, no surprise topping the list at almost 80% was meeting all the safety requirements and processes for automotive applications. This is not a trivial task; this is something semiconductor partners have invested in for very many years. But along with that, the compute requirements are going up so high that optimizing the power for a given performance is also becoming equally important. At Synopsis we're looking at these challenges and designing solutions to these challenges. One of the things I wanted to do is take a quick case study in terms of ADAS. ADAS is one of the most popular and growing applications within the overall automotive. As I said, no surprise in the ADAS chips, safety is mission critical because it is all about helping the driver to be more safe, but also power is really important within an ADAS chip simply due to the fact there is so much functionality going into an ADAS chip: the vision processing, the amount of on-chip memory and so forth is just exploding. So you really have to look at your power envelope.
We have invested very heavily at Synopsis in automotive IP. We have a very rich portfolio of IP that's been certified for ASIL B or ASIL C or ASIL D depending on the particular type of IP. It's also ISO certified; our entire development processes have been certified by independent external auditors. This is something we have taken very seriously and have invested very significantly in creating a very wide range of what we call automotive grade IPs, from the processors and I'll talk about an example of that next, to memories and logic libraries, to interface IPs such as Ethernet and LPDDR and PCI Express and HDMI and USB, to integrated safety and security IP which is what I'm going to be talking about here on the next slide.
One of the things we have created to help our automotive customers is we've created a functional safety solution that is ISO 26262 compliant for automotive. At the heart of it is a safety island based on our ARC processors. We have multiple cores running in lockstep looking for errors. This is just not at boot time; this is at real time, constantly monitoring every five to ten milliseconds as a car is in operation, looking for any kind of faults. Then we have a dedicated test network that is being driven by our embedded test applications such as SMS, our memory system, and SHS. What we do is we work with our customers to put these safety wrappers around the IP that's already automotive grade certified, and then we create code that then runs onto the safety manager. The whole system here is continuously looking for faults and taking corrective action if it does find a fault. This is a fully integrated solution from Synopsis that's really going right at the heart of some of the things needed by ADAS in terms of ensuring the safety of the vehicle.
Now I wanted to also just conclude this presentation by saying we've had a lot of success in automotive and we've been fortunate to partner with some of the leaders in this industry, including Infineon in their next generation or 3D platforms, including Qualcomm in their relatively recently announced Snapdragon Ride platform, and here in Israel, Arbe Robotics, who is a leader in high resolution imaging radar. We work very closely with them to have the highest levels of safety for their chip. We're having great success in automotive. We have a very broad portfolio, we're working with many excellent customers, and we're continuing to be committed to drive this forward and continue to evolve. With that, I just wanted to say Synopsis is really your trusted IP partner. We have complete solutions. We have the broadest portfolio of IP on the market. We're dedicated to the highest quality of IP. We have a small army, some people might joke a large army, of 4,500-plus engineers working on IP. We're really going after and doing what it takes to be successful in all these new areas we talked about, whether it's automotive or cloud or server high performance compute, IoT, 5G, and so forth. With that, I want to thank you very much for your time and your attention.