1.1 - Semiconductor Industry: Present & Future (Kevin Zhang)

Thanks, Frank. Thank you, Frank. Good morning, everyone. It's such an honor to be here to have the opportunity to share our view on the semiconductor industry, present and the future. As Frank mentioned earlier, I'm a long-time member of the ICCC community. I served as the virtual conference chair for two years during the pandemic. So I tell you today a little secret: I wish I will be the only one to remain the only virtual chair in ICCC history. My association with ICCC actually started over 25 years ago, so I'm showing my age now. When I first attended the conference as a newly minted PhD, I remember I was totally in awe by the magnitude of the conference, the breadth, the depth, and the quality of the presentation. So I sat way back in the room tentatively listening to all the presentations. So today I want to speak to all the students and the young engineers in the back. I'm the living testimony you can make it all the way up here, but it takes a lot of hard work and some gray hairs.

So let's talk about semiconductors today. We all know life runs on semiconductors. Semiconductors truly have become the foundation for the modern economy. Anything we do relies on semiconductors. I bet everybody has different semiconductors in your pocket right at the moment. So from high-performance computing, AI, machine learning, to communication, from transportation to healthcare, you name it, everything depends on semiconductors. Since I'm wearing a business hat these days, I want to talk about semiconductors a little bit from a business perspective. As you can see, today worldwide semiconductor revenue is about $500 billion, half a trillion. So it's a common consensus by the end of this decade this number will double. But I have to add a qualifier here: given the recent surge of AI, the $1 trillion number does not reflect the multi-trillion dollar Sam Altman of OpenAI plans to invest in semiconductors. It doesn't reflect the latest projection from Lisa Su of AMD talking about a $400 billion AI market alone by 2028. It's bigger than iPhone. I think nobody knows exactly how AI is going to shape this growth curve, but one thing is certain: we are entering an accelerated growth period for semiconductors going forward.

If you take a little bit deeper look on this potentially $1 trillion market, high-performance computing (HPC) takes the top position, equalling 40%. It equalling the mobile combined with IoT. Just a few years ago, this was unthinkable because the conventional wisdom always believed it was the edge devices where you consume the most silicon, but no more, thanks to the surge of AI. Talking about AI, I have to talk about ChatGPT. Since the introduction of ChatGPT over a year and a half ago, we're already seeing the landscape changing in the semiconductor industry. If you look at this steep curve, what's behind this steep curve is really the insatiable demand for energy-efficient compute. So Jensen Huang, NVIDIA CEO, said ChatGPT is the iPhone moment for AI. Sam Altman of OpenAI said the new Moore's Law is AI: the total intelligence in the universe gets doubled every 18 months. You can describe AI in different ways, but one thing for sure: it requires a lot of advanced semiconductors, more than everybody can imagine.

Today, let's talk a little bit about communication. Wireless communication is very important in our life. Here I show you three connectivity technologies: from cellular to Wi-Fi to Bluetooth. As you can see, all the advanced standards require a higher data rate, more advanced signal processing. This will continue to drive the accelerated adoption of advanced silicon technology. Using Wi-Fi 7 as an example, actually this year we're moving into the production of Wi-Fi 7. From the get-go, Wi-Fi 7 has to adopt 7-nanometer technology in order to achieve the power performance targets.

I want to talk a little bit about automotive. Automotive is really going through a fundamental evolution. Lots of people call the new automotive 'software-defined automotive,' but I think the better term is 'silicon-defined automotive.' The reason is, software has to run on silicon, and you see there are lots of silicon right from sensors, connectivity, network, and to the most advanced semiconductor technology to drive the autonomous capability going forward.

Before I dive into the technology discussion, I want to take a moment to talk about the business innovation of the semiconductor industry: the introduction of the pure-play foundry model. This was pioneered by Dr. Morris Chang over three decades ago. This innovation has fundamentally changed the landscape of the semiconductor industry by taking out the very complex, costly technology manufacturing out of the traditional IDM model, allowing IC companies to focus on their product development, focus their innovation. By working together with the foundry, actually we greatly accelerate the innovation in the whole industry. Because of the introduction of the foundry, there are lots of new players that occurred, and the fabless companies flourished. Fast forward to 2030, as you can see, over 50% of the semiconductor revenue will be contributed by the fabless companies, the system companies, or cloud providers. That's all because of the business innovation, the emergence of the foundry.

So now let's talk about the technology. Transistors remain at the heart of the innovation, silicon innovation. The transistor has gone through a significant evolution over a few decades since it was invented over 75 years ago. So as you can see, in the early days, transistor innovation largely centered around geometry reduction, but that's no longer the case. In recent generations, it's all focusing on the innovation in the transistor architecture and the use of new materials. For example, at 16 nanometers, we moved from planar transistor to the FinFET transistor. And today, we are at the dawn of introducing a brand new transistor architecture at 2 nanometers called nanosheet. By wrapping around the entire channel with a gate control, you actually greatly improve the electrostatics of the device, improve the conduction, and provide a better capability to operate at even lower voltage. This is very, very important for high-performance computing.

Talking about patterning technology, the introduction of EUV at the 7-nanometer actually paved the way for us to continue driving the geometry scaling going forward. So you may ask, what's next? I would say, first thing first, actually we need to milk this nanosheet transistor for a couple of generations to extract the best value, the maximum value, after this new transistor architecture. But at the same time, our technologists are already busy making a brand new transistor architecture. Here I show you one promising example called CFET. Essentially, by stacking the NMOS and the PMOS on top of each other, you can greatly improve the density by nearly a factor of two. And on the material front, our technologists continue to work on new materials like low-dimensional materials. By introducing these new materials, we think we can achieve even more energy-efficient switching devices well beyond today's devices or transistors.

This is a little bit further look at what the benefit of CFET can bring to you. As you can see, in the logic case like an inverter, you can stack NMOS devices on PMOS devices. The same thing can be applied to the 6T SRAM cell. In doing so, you get nearly 2x of the density enhancement. Very, very significant. This is no longer a simple idea on a PowerPoint. Actually, here I want to show you a TEM picture. This is the real integrated device that has been fabricated in our lab, and here you see the transistor IV curves. They're beautiful curves. So this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.

As we shrink the geometry of the transistor, it's getting harder and more costly. Designers and technologists have to work together in order to achieve optimum scaling benefit at the product level. So we often refer to this so-called design-technology co-optimization, or DTCO. Here I show you one example in the digital library design on the FinFET technology. By using a so-called technique called depop, reducing the number of fins per cell, you actually can reduce the cell geometry and at the same time lower the power consumption. But when you reach the two-fin-per-device, the designer faces a difficult time or dilemma. If you go further, you will incur a severe penalty in the speed. By DTCO, by innovation, actually our design and technology team worked together to come up with this new idea we call FinFlex. Essentially, it allows designers to mix and match single-fin devices, two-fin devices, or two-fin versus three-fin, so we can achieve optimum performance, density, and power consumption at the same time.

Talking about DTCO, another good example is really about the SRAM bit. Here I show you the SRAM scaling from 13 nanometers all the way to today's 3 nanometers. We achieved over 100x density improvement. This scaling is really the result of a collaboration or combination of process innovation and adoption of more advanced design techniques. I don't know how to partition who has done how much, but I often tell my folks, technologists and designers, you are just equally important.

Talking about SRAM, you have to talk about the minimum operating voltage, or Vmin. In the good old days, in order to lower the voltage, you had to adopt a larger memory cell. But that's no more. By applying innovative design techniques, in this case, like a negative bitline assist technique, you actually can achieve over 300 millivolt Vmin improvement. This is very significant for low-power operation.

So I talked a lot about technology scaling. The essence or the objective of technology scaling, in the end, really comes down to this: energy-efficient compute. So the industry as a whole, we've come a long way. Here I show you the scaling just over a little bit of a decade. We achieved over 80x energy efficiency. This kind of advancement really enables today's emergence of AI. So people in this room should be very proud of how far we have come along.

So let's talk a little bit more about the technology platform for HPC or AI. If you look at today's all the so-called AI accelerators, whether it's GPU, whether TPU, or customized ASIC, all essentially feature this particular integration scheme. Basically, you use a CoWoS chip-on-wafer-on-substrate, bringing the advanced piece of silicon, today mostly 5-nanometer technology, and high-bandwidth memory together. But this is not sufficient going forward. This platform needs a significant uplifting to address the future high-performance computing needs. So in the heart of this configuration here is really higher-density, low-energy compute. So you need to go to stacking in order to achieve computation density. So you need to stack vertically multiple most advanced silicon pieces together to provide the computation density required. And you need a lot of memory bandwidth, so you need to bring more HBM into the package. So the interposer or CoWoS has to expand further in order to comprehend this. But that's still not enough. The power delivery is a problem, so you need to integrate voltage regulators in order to solve the power delivery challenge. And IO and bandwidth interconnect density become an issue too. So for that, you need to bring silicon photonics into the package. So this is where the future is going. There are still lots of challenges in order to bring, for example, the co-packaged optics closer to the electronics die, but the physics tell us this is the future.

So let me talk a little bit more about the 3D stacking. Here I show you the interconnect density. Because stacking, the reason we go to stacking is really to achieve high interconnect density or chip-to-chip communication. These two curves show: the top is essentially the monolithic interconnect density, the bottom is the conventional packaging density. You can achieve the middle, obviously, which is CoWoS, often called the 2.5D solution. But going to the 3D solution, we call SoIC. By doing that, by aggressively scaling the bonding pitch all the way down to a couple of micron range, you actually can achieve the interconnect density like monolithic. That's why the 3D is the future.

Let's also talk a little bit about silicon photonics or co-packaged optics for the future high-performance computing. We know electrons are very good at computation, but photons are better when it comes to signaling or communication. Here I use a 50-terabit switch as an example. It's everything is electronic, it's a coherent system. This system will burn up to 2400 watts. Today's solution is you convert photons at a board level by using so-called pluggable optical transceivers. You actually can reduce power by 40%, but this is not sufficient. The future requires more high-speed signaling, more bandwidth. So in the future, you need to convert electrons to photons much earlier inside the package. So you need to bring the photon capability, using advanced packaging technology we call co-packaged optics. In this particular case, you have to also leverage advanced stacking to bring the photonic die and the electronic die together. By doing so, you can cut down the power consumption by 50%, achieve roughly about 5 picojoules per bit. So this is where the future is going.

So today, using the most advanced transistor technology, you can pack roughly about 100 billion transistors in the same die. I'm not talking about small die, I'm talking about pretty big die. But this is not sufficient to address the future AI machine learning application. You have to leverage advanced packaging, 3D technology, to really pump up the number of transistors to trillions of transistors to address the future computation need.

I want to talk a little about cellular. If I remember, when I was chairing the memory subcommittee at ICCC, I was always jealous about how many big audience RF papers can always draw. So I do pretend to be an RF person and talk a few things about RF from a technology perspective. So let's go back to the 4G to 5G transition. In order to improve the data rate by tenfold, you need to incorporate a lot more digital circuitry, like advanced ADC, advanced signal processing capability. So in doing so, RF transceiver design actually can benefit greatly about moving from 28 nanometers to 16 nanometers back to the 4G to 5G transition. But if you look forward to 6G, for example, you need to cover a broader range of the frequency, like FR3. You need to pump up the data rate another tenfold. So this will require even more advanced semiconductor, more advanced computation technology. So you would not be surprised to see the future transceiver design will be based on 7 nanometers or even 5 nanometers.

I want to talk a little bit about automotive. Automotive is a very, very exciting area. If you look deeper at automotive, fundamentally it's really bringing a lot of computation power into your car to support autonomous driving. Today we are really at the beginning. In order to achieve, I call it 'eyes off, minds off,' you really need over thousands of TOPS in a car. But the power consumption is becoming a real problem, especially for battery-powered cars. One of my friends working in a leading auto OEM tells me he's the most hated guy in his company because all the other guys push hard to save every bit of energy to let the car run a few extra miles. But when he brings more powerful SoCs, more powerful AI, it literally wipes out all the gains other guys have done. So I told him, 'Hey, you need to go to advanced silicon technology. How about 5 nanometers, 3 nanometers?' Not so fast, not so fast. There is a good reason why the silicon technology for auto has always stayed back a couple of generations behind consumer or HPC. That's because of very stringent safety requirements. The defect density requirement for auto applications is basically near-zero DPPM. To achieve that level of DPPM, you need to run millions of wafers for years to achieve low-level defect density. But that's not fast enough to address the future automotive requirements. So foundry, semiconductor manufacturing, and auto design folks have to work more closely going forward to accelerate that pace. A couple of things we're doing: for example, we apply auto design rules upfront to reduce the defect density, and we're applying at time zero more intelligent dynamic voltage stressing to basically screen out the potential defective parts and provide fast feedback on failure analysis. So in doing so, now I see clear paths we can accelerate the adoption of more advanced technology for auto applications. So here I'm speaking to my favorite crowd, so it's my commitment to all of you: you will see 3 nanometers in your car before long.

So talking about automotive silicon technology, I have to talk a little bit about MCU, which features embedded non-volatile memory. This is very important. MCU becomes more important as auto transitions into the zonal architecture, where you really need advanced silicon technology to provide computation power for MCU. The traditional MCU largely featured floating-gate-based technology, but floating-gate scaling at 28, 9 nanometers ran into the wall. It takes 8 masks to integrate the floating-gate cell into the logic technology. That clearly is not viable going forward. The good thing is the industry has invested in this new memory technology, we usually call emerging memory technology, like magnetic RAM or resistive RAM (RRAM). It turns out that this emerging memory actually emerged in time to intercept the future MCU technology. So by moving the MCU to MRAM-based, RRAM-based technology, actually you can see we can continue to drive the technology scaling quickly, going down from 28 to 16 and the future to 7 nanometers.

So I want to talk a little bit about sensor and display. We always say logic technology is the center of this digital transformation, but the world we live in is analog. The physical world is analog. So sensor and display technology play an essential role in bridging the real world and the digital world. So the integration of digital cameras with smartphones actually fundamentally changed how we document and communicate our life. As you can see, over a trillion pictures are being taken now per year. It's a very important technology. The sensing technology has evolved substantially over the years, from simple two-dimensional, single-layer design. Now we have this smart system based on 3D wafer stacking. Basically, you stack the signal processor layer wafer on top of the sensing layer. Going forward, our technologists already started investing and researching on the multi-layer design. The reason for doing this, I show you a couple of examples for the pixel optimization. One of the key benefits by doing three-layer or more-layer design is you can split the photodiode and the transistor into different layers, so you can optimize the pixel without shrinking the collection volume. Photon collection volume efficiency is very important. Then you move the transistor on the other layer. So this is where we can continue to drive the pixel scaling to achieve the resolution requirement, but at the same time achieve optimum sensing capability. Another good example on this multi-layer sensing approach is for AR/VR, where the form factor is a paramount requirement. So by splitting the storage of the different layer and stacking on the rest of the logic, you can effectively shrink the geometry and at the same time maintain the high-performance requirement.

So now I would like to conclude my talk by looping back to the economics of semiconductors. We talked about this $1 trillion market by 2030. If you really want to size up the impact of this $1 trillion semiconductor, you have to consider the multiplication effect. This $1 trillion in semiconductors drives up to $3 trillion in electronics industry and generates $12 trillion in IT revenue and creates over $145 trillion in GDP. So the economic impact from semiconductors is enormous. I want to share a little bit of a personal anecdote with you. Seven years ago, I left the then-largest semiconductor company to go to Taiwan. At that time, I was thinking my best time in semiconductors was behind me, so I was just going to Asia to sunset my career. But fast forward seven years later, instead of seeing a sunset, I see a bright sunrise. With the emergence of AI, semiconductors are going to power so many new applications. It's going to touch every aspect of human life and change the trajectory of human history. So I see a bright golden era right in front of us. There has never been a better time to be in the semiconductor industry. Our best days are still ahead of us. Let's work together to make it happen. Thank you for your attention.