Vice President of Engineering, Qualcomm
2023 ERI Summit: International Supply Chain (Chidambaram)
Dr. PR “Chidi” Chidambaram, Qualcomm Vice President of Engineering and Fellow, presents "Semiconductor Technology and Supply Challenges."
About Chidi Chidambaram
At the 2023 ERI Summit, Qualcomm Vice President of Engineering Dr. PR "Chidi" Chidambaram discussed semiconductor supply chain challenges. He stated that the electronics industry has shifted from producing thousands of units to billions, with a modern smartphone containing about 70 components. Chidambaram noted that 50% of worldwide wafer capacity for legacy logic planar technology is located in China, as companies in the United States migrated to newer nodes rather than maintaining older capacity. He said that Qualcomm considers supply resilience a core aspect of chip design and attempts to multi-source and balance sourcing from different geographies based on market sales. Chidambaram highlighted the industry's vulnerability to disruptions in Taiwan, stating that a power outage there could cost Qualcomm $4 billion and the industry nearly $50 billion, with flooding in Hsinchu potentially costing $21 billion and an earthquake up to $50 billion. He also suggested that government investment in 450-millimeter wafer technology could be an interesting idea, though he noted the equipment industry is reluctant due to high investment costs and a 15–20 year recovery period.
Transcript (26 segments)
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Chidi Chidambaram0:00
It's a true honor to be here. I really learned a lot about how the government research programs work. Thank you DARPA for inviting me.
So if you want to understand the supply chain in the electronic industry, the key thing to understand is also scale. If you look at the electronic industry in four groups: 40 years ago it was IDMs. We were dealing with thousands of units. It was all built in an IDM in the same place, everything came from one factory. They had this packaging there.
Then Qualcomm came along 20 years ago and expanded the scale of the industry from thousands of units to millions of units. With the cell phones, we had to go fabless and started working with fabs and OSATs, but we were still shipping millions of units.
But today, with the advent of AI and a few other things, we are building a lot of complex systems. It's truly systems engineering. It's no longer a few chips in a cell phone. For example, we have about 70 different components that all make up the supply chain. We have to have every single one of them to be able to ship the phone, and we are shipping them in billions of units. That's the other thing that's changed the equation in the supply chain.
So I want to talk about what are the systems we are building and the system complexity that comes from it, and how the semiconductor landscape that exists today, where are the kind of capacities that exist in the leading edge and packaging and things like that. And a couple of key ideas. It's very hard to solve supply problems, but I'll show you one or two ideas that we have on how we ensure supply resilience.
So to start with, we had a lot of conversation today about generative AI. There's about 175 billion parameters. Even in edge implementations, we can get up to seven billion parameters. To accommodate this, we have flash and DRAM and a lot of components that have to change to make this a fundamentally successful implementation. Bill, Naveen, Mukesh, and many others talked about this. I don't want to spend too much time talking about generative AI, but the key is the attention. If you look at what makes human beings different from other animals, I can look at a room full of people but I still know I got 12 minutes left. The attention that you can focus is what makes human beings different, and bringing that into the Transformer architecture helped generate a lot of new applications that's really taking off.
And the connectivity is another important piece. Our cell phones today are 5G, but not too long ago we were doing 3G and 4G, which was primarily used for talk. We went from 'are the calls dropping, can you hear me' to they were more robust and things were functional. But as we go to 6G, you're going to have a lot of things-to-things connections, and these all exist in very different bands. If I take your cell phone to Japan, it might be 3.9 gigahertz, and if we go to Korea it may be 2.4, and then you come to the United States it's 1800. For handling all these different bands in every place, you are adding components to your supply system that makes the whole system extremely complex.
And if you take an automobile, where Qualcomm is putting a lot of effort in and we have a lot of traction in this space, if you look at a roadside intersection, there is a roadside unit, RSU, that's operating like the expert system. There is a car with certain chips, and there is a pedestrian with a cell phone in their hands, and all of them can talk to each other. We use C-V2X protocols to intercept each of these. Today in 5G, with about six microsecond latency and the connection density guarantee, you can implement them in smart cities as a safety feature. But if you fast forward to 6G and reduce this to a two microsecond, you can actually have the roadside intersection manage the intersection such that nobody has to stop. It's possible because the latency and the connection density and the guarantees will become possible. So a lot of exciting things happening.
And in order to put all this together, you can look at how complex the supply needs to be. I've divided them into four groups here. The vertical logic technology, everyone talks about this, is kind of like the gate-all-around or the FinFET technology, which are super high capacity, capex needed. But if you look at the total number of wafers that Qualcomm buys, we actually buy a lot more in the planar logic and the RF, where we build our power management systems, audio codecs, and transceivers in the radio frequency.
We also need a lot of passives. We buy inductors, they are sometimes built on the package, sometimes they are surface mount devices, SMDs. And we do capacitors. Some of these capacitors are integrated with the die, some of them are surface mount devices. So that's what makes up all these 70, 80 components that we need.
So if you look at the breakdown of where we get things from, everyone knows that there's only 12% of the capacity to build semiconductors in the United States today. People from Commerce talked about this before. In the 1990s it used to be 50, 60, or 70 percent, and then it came down to 12% now. And the goal of the CHIPS Act is to get back to 50 percent.
But most of this is categorized here as memory, logic, and discrete analog. The important thing I also want to point out: if the total capacity, the trailing nodes it says is 33%, and the analog and RF power says is 16%, so together that's 50%. So if you look at the world of where wafers are being produced, about 50% of them are in older nodes. There's only 14-15% in the leading edge. I think it's an important point I want you to remember.
And if you look at the vertical advanced technology here, it's mostly Qualcomm. We're getting most of our stuff from Korea and Taiwan, and Taiwan is a very significant source. This is one of the major concerns for us. If there is a power outage in Taiwan, we lose 10% of the capacity, that's like four billion dollars for us and almost 50 billion dollars for the industry. If there's a flooding in Hsinchu, that's 21 billion dollars. And if there's an earthquake, lo and behold, that's almost 40-50 billion dollars. So we're extremely sensitive to what happens in a small island, which is not an ideal state to be in.
And so the logic planar technology is the interesting one. I told you 50% of the worldwide capacity on wafers is in this logic planar or legacy technology. When these were built 20 years ago, Intel and a lot of the companies in the United States were in the business of building wafers at that time. Their model was they would build them in 65 nanometer node, and when 45 nanometer node came along, they'll shut that down or move the tools to 45. So there's really no capacity that exists in these nodes because they were migrating them all the time.
And as the complex things I showed you in the semiconductor chart, in all these industrial automation and AI and all of them grew, we needed these power management and other chips. And guess where the capacity came? Because nobody was willing to put new money into an older technology anywhere other than China. So a large part of this capacity ended up existing in China, and that's where it resides right now. It's one of the big challenges because the center of gravity of the legacy nodes is mostly in China.
So the DARPA team asked me, they want to hear innovative ideas on what we can do. So I put some innovative idea. By the way, the equipment industry doesn't like this idea. Let's say we invest the dollars into a 450 millimeter wafer technology, which was talked about and invested in almost 10-15 years ago. But let's say we do that today. It's very hard to do that in deep UV, nobody's going to build a deep UV at 450 millimeter, but deep 193 is possible and others are possible. So if we do that, we can bring back the manufacturing with that investment. But the equipment companies don't like it because they have to invest a lot of dollars into this and it will take them 15-20 years to recover the cost. But if there's government investment, that might be an interesting idea to consider.
Let's talk about advanced packaging. The 'advanced' in advanced packaging is really something that the foundries are kind of cannibalizing the packaging market in a way. If you think about it, they want to bring patterning, they want to bring class one clean room type operation, which enables new features. But is that the only answer? If you look at the R&D dollars that has gone into advanced packaging in the last 50 years, Intel has got some innovative things that are cost effective. I really like the EMIB and other approaches that Intel has developed. But if you look at the rest, it's a lot of very expensive technology in a field that we're not sure if it needs to be that expensive.
So I'm hoping with this APMP and all of the government activities, there is a more multi-dimensional R&D that enables a lot of cost-effective solutions. In Qualcomm, we would love to use chiplets and we would love to use it, but today it's so expensive it doesn't make sense. And it doesn't have to be. I think the R&D dollars were not spent in a uniform way to see what other opportunities exist. And I hope with DARPA and the CHIPS Act and others, we're going to make some investments that make this cost-effectiveness become reality in the advanced packaging space.
Okay, so some ideas. I don't have many, but I'll show you a couple of them. Of course, chiplet technology is key. And so far, if you look at the last 20-30 years, we've met our user experience. Qualcomm has shipped a phone every year, and every year the reason people buy our phone is mainly compute power reduction. So we've focused the user experience and battery life improvement coming from compute power improvement. And it's really process technology, as you know. I would say not all of it, probably 20-30%. Bill said in NVIDIA's case, they only got 2.5x process technology improvement in a span of 12-15 years. For us, it's probably a bit more, probably 40%.
But what do we do if that's not going to be there? We can substitute it with these connection density improvements. That's part of 3D, everyone talks about it, chiplets. But to me, I can't use it because it's too expensive. Nobody is going to pay twice the amount for a cell phone and buy it just because I got 3D stacking. So we got to figure out how to keep this thing in a cost-effective manner and how we can do it. I think there are lots of ideas, and I think in the next two-three years it's going to happen.
So if we do that, then we take away from the leading edge node. Part of the advantage I get is the leading edge nodes are increasing in cost. The cost per gate forever, mostly, I said that the cost per gate is going to keep going down, which it was. But in the last two-three years it's turned around and it's going up. So if I don't go to the latest technology, my gates become cheaper. I can keep them at an older node and stack them, and I can save some money. And it also gives me some flexibility. I can go to different places to build different chips. So that's one idea.
But to continue this idea, I want to give you the thought how complicated it's going to be. Because on one hand, the process technology itself, the extension of Moore's law that is shown on the top, is taking a lot of chiplet kind of concepts. There's going to be stacked gates like CFET, which is a vertically stacked N/P transistor, which also uses some stacking technology. Then there is backside power, which uses some kind of stacking technology. So how am I going to make that live with the regular chiplet technology that also talks about stacking? It's not very easy. So these two axes somehow have to marry with each other and become very cost-effective for me to actually take advantage of them and use it.
So the other strategy that we've used is what we call multi-source the same chip. In fact, Qualcomm became a leading fabless company mainly because we were able to, as a fabless, get multiple sources to do our chips. There were people in 2010-2012 who thought fablessness cannot grow to be very large size because they have to be very supply constrained. But we innovated and broke that paradigm by shipping our dice to different factories. We take the same GDS and we can manufacture at almost six different foundries and 12 different factories. So there's a lot of innovation that goes into it, how to make this happen, how to get the foundries to match, and how to do this.
So we can do this in the legacy nodes, but when you come to the mid-range early FinFET nodes, we do what's called core timing. We keep the same GDS, same floor plan, but we time it with two different timing models, and then we do ECOS to make sure they're going to function. And then if you go to the very latest node, gate-all-around, there's no way to do anything like this. So we just kind of pick one or ping-pong with each other. That's how we multi-source and ensure our supply resilience.
So in summary, supply resilience has got to be a core aspect of how you think about your chips. If you want to do the latest and greatest and all the features, you may not be able to keep the supply resilient. So at Qualcomm, scale is a fundamental DNA. So we always, when we pick our choices and how we do things and whether we do chiplets or not, we always think about what kind of scale can we do. And multi-sourcing is possible, and the chiplet technology offers some advantages here. But we try to maintain a balance. We kind of look at our market, how much we sell in each geography, and source from that geography to the same extent.
But it's still not everything can be solved. So supply is more complex than PPAC. Thank you very much.