[36] TSMC Technology Interview: A16 Node, System-on-Wafer, and High-NA

Pleasure.

Well, I think my simple answer is I don't care. As long as we can continue to drive the technology scaling, I don't care if Moore's Law is alive or dead. But you know, reality is lots of people narrowly define Moore's Law based on two-dimensional scaling. That's no longer the case. If you look at the innovation in our industry, we actually continue to find a different way to integrate more function, more capability into the small form factor, continue to achieve higher level performance and a higher level of power efficiency. So from that perspective, I think Moore's Law or technology scaling will continue. We will continue to innovate to carry the industry forward.

That I leave somebody else to define.

Well, I don't particularly like the word incremental. If you look at our technology roadmap, you know, from 5nm to 3nm, or from 3nm to 2nm, if you look at energy efficient improvement, it's not incremental, over 30% per generation. But in between the major node, we are continue to drive the incremental enhancement. The reason we do that is we allow our customer to continue to harvest each new generation of technology in terms of a scaling benefit. So between major nodes, yes, we continue to drive the incremental, but between the major nodes, actually the enhancement or the power, performance, density improvement is very substantial.

Correct. Correct. For example, 5nm, right? After our customer move to 5nm, they can continue to leverage the incremental enhancement from N5 to N5P. When you get the performance boost, then you go to N4, N4P, you can further densify the improvement. So those incremental enhancement after you jump on the major node allow our customer continue to harvest the scaling benefits and the investment they make upfront.

Well, you know, we work very closely with our customer to pick the right technology node to intercept their product. This is often based on specific product design to see where they can most achieve their optimum device level, the product level benefit. So we work very closely with our customer to make the right choice.

No, we don't want surprise customers. We actually work very closely, very open with our customer to make sure they choose the right technology. Remember, we are in a foundry business model. Our goal is really to help customer to achieve successful product. My boss often tell me, Kevin, you know, we're in the foundry business, we work together, we achieve success, but there is a sequence. Customer has to succeed first, then we can be successful.

Yeah, yeah. So, you know, A16 is a major technology enhancement, or revolutionary, in terms of bringing further power performance to future high performance application, especially targeting for HPC and AI. A16 features nanosheet transistor, which is the industry leading, most advanced transistor architecture. But at the same time, we add a very innovative backside power rail design. This backside power rail design allow design customer to move the power supply routing from the front to the back, open up space, allow to enhance the performance, same time improve the power supply. This is particularly important for very high performance system design because power delivery has become very, very important, critical. We talk about in a small form factor you have to bring close to a few hundred watts, so the IR droop become very, very significant. By moving the power rail to the back side, you actually significantly improve the integrity of the power supply rail. Our approach is very different from the conventional design. The conventional backside power rail basically you just drill a hole, connect the backside metal to the front side metal, you burn space, right? You have to enlarge the footprint of the library cell. But in our design, we have very innovative approach. Essentially we move the contact of transistor, the source of the transistor, to the back without changing the footprint of the library cell. So this clever way allow us to maintain the footprint, provide the maximum flexibility to our customers.

Definitely, definitely will have a cost associated with. But if you look at the density, power, performance benefit, I think it's outweigh the cost. This is particularly important for HPC and AI application where energy efficient compute is the king, is the driver.

A16, by definition, will have the backside power, we call Super Power Rail, yes. But we do offer the technology option allow a customer continue to leverage the existing design collateral, don't have to use the backside power. For example, for mobile application, you don't, where the power supply, power routing is not as intense, you don't have to use the backside power rail.

We're targeting second half of 2026 going into production for our A16 for the lead customers.

Well, I don't think I want to get into detail into collateral schedule, but in general our collateral schedule is designed to target the customer production date introduction. As we said earlier, we target A16 going to production by second half of 2026, so our collateral schedule will support that kind of schedule.

A16 will start in Taiwan, yeah.

Yeah, yes, this is a very innovative approach. You probably heard about design technology co-optimization, DTCO. This is where we continue to drive the collaboration between design and technology in order to further optimize our technology offering to provide a better scaling benefit. So FinFlex you mentioned earlier, because in a FinFET transistor architecture, the number of fins is digitized. So in the past, before this innovative FinFlex approach, you have to use either three fin or four fin, you can't swap them easily. So our FinFlex technology at 3nm allow designer to mix and match different fin based library design. But for the nanosheet, we call NanoFlex, this is effectively similar idea, allow the designer to mix and match different height of the library, different sheet width based on the nanosheet width. So you can alternate different size, different height of library, allow design to choose and pick based on specific design target to achieve optimum benefit in terms of power, performance, and density. Very innovative approach.

That's on top. That's orthogonal to the height of the library. So you can go NanoFlex and VT.

First thing first, CoWoS is today the workhorse for AI accelerator. If you look at all the AI accelerator design, pretty much today they all base on TSMC 5nm or 4nm technology plus CoWoS. CoWoS is in high demand, everybody can spell CoWoS these days, even the TV reporter can do that. So obviously last year the AI surge took a lot of people, including ourselves, by surprise. The CoWoS demand has surged tremendously over last year. We are rapidly expanding our CoWoS capacity now. I think the growth we're talking about, well, about 60%, very, very, very high, but still the demand continue to grow. We work very closely with our customer to make sure we provide their most critical need.

If you look at today's state of the art AI accelerator, the CoWoS interposer size roughly about 3x of the reticle size. Reticle size about 800 mm square, so that provide the capability to integrate a full reticle size silicon along with up to 8 HBM. But in the future, just two years from now, we will have the ability to expand the interposer size to 4.5x of the reticle size, allow our customer to integrate up to 12 HBM. We're not going to stop there. Our R&D team already started expanding the CoWoS interposer beyond that to 8x of the reticle size. So very exciting area.

So that's actually, this symposium we also announce another innovative system level integration technology we call System on Wafer. Essentially you think about it, the maximum size you can do in a wafer processing facility is a wafer, it's a 300mm wafer. So we take the wafer as our base layer, we can bring all the logic and high bandwidth memory together to integrate along the wafer, the whole wafer area. So this, if you measure using CoWoS terms, the number of X of interposer size, it effectively give you 40x of the interposer size. So humongous. So this is really provide our customer to continue to integrate more compute function, more memory bandwidth to address future AI requirement.

We work very closely with our customer. So we do wafer level integration and the customer obviously have to design the back end, the system level in terms of how to bring the cooling into the system. It obviously involve lots of collaboration. We work very closely with our customer and the system provider to basically work together to find the optimal thermal solution.

Well, we already have a limited production, but in the future, as you pointed out, there are going to be more AI high performance customer want to leverage wafer level integration to address their future needs.

I hope we don't have to reduce the reticle size because what we see is people want to integrate them all function closely together.

Sky is the limit. Sky is the limit. I think we continuous to see the trend, the demand for energy efficient compute, it's just insatiable, right? We're talking about the AI model, ChatGPT model, ChatGPT-4 already use a trillion variable, in the future even more. So think about the computation requirement, it's amazing. So we continue to expand our capability. Transistor level, obviously we have 3nm, next year we're going to 2nm, then we have A16. We continue to drive the energy efficient compute at the transistor level. Same time, sometimes we talk about CoWoS expand and wafer level integration. I think putting all this together, by the way, we also bring the optical signaling into the package, right? So putting all this together, really we're talking about provide customer a platform allow them to integrate more compute function, you know, more memory bandwidths all together to address the future AI requirements.

Stanford. That's how COUPE Stanford. Yeah. So we have been doing silicon photonics for quite some time actually. We fabricate components and our customer put the silicon photonics together with electrical transceiver to form the so-called optical pluggable transceiver, has been widely used in data center. But what we're doing today is we take one step further, leveraging our most advanced 3D stacking technology we call SoIC. Essentially using the hybrid bonding technique to bring the electronic die and photonic die closer together to form a small form factor optical engine. That's where you basically do the electron-photon conversion. We know electron is good at compute, but photon is better when talk about the signaling. So by building this compact optical engine, then we integrate into the advanced packaging, whether it's today's probably the substrate, in the future could leverage something like a CoWoS to bring them together to significantly improve the bandwidth and power efficiency. If you look at today pure copper all electronic system, the switch, 50 terabit switch, it burn over 2,000 watts. By using this tiny, small form factor optical engine, we actually can bring the power down by at least 40%. So this is a very, very efficient in terms of achieve high data bandwidth at the lowest possible power.

Yeah, I think the key is to bring them together because the compute still has to be done by electron.

Yeah, it's difficult to mix a photonic feature on the advanced electronic die. It's difficult to do a monolithic. I think by using our hybrid bonding technique, we achieve the kind of connectivity, power efficiency, like almost like a monolithic, but same time allow us to optimize the electronic die and the photonic die separately. I think this is, you get the best of both sides of the world.

The pluggable version today, actually if you look at the data center today, the prevailing way to do this is using pluggable at the board level. So you convert from electron to photon at a board level. So in the future, you convert within die. So the signal coming after the die, you turn electron to photon. So that's where you get the efficiency.

It is a pluggable. The optical, the fiber plug into your die.

If it's in, it's in.

Well, maybe let's step back. Let's don't forget TSMC is the leader in terms of bringing EUV into high volume manufacturing back to our 7, 6 nanometer generation. We're the very first in the industry to bring EUV to a high volume manufacturing environment. I think we're still the leader today in terms of EUV use and production efficiency. I think our R&D team will continue to look at it, the new EUV capability including obviously High-NA EUV, and we're going to pick the right place to intercept our technology node. There are lots of factors you have to consider, right? There is obviously the scalability factor, there is also a cost, manufacturability factor. So I trust our R&D team will make the best decision where to choose the next generation EUV to intercept our future technology.

It's progressing very well and very fast too. If you look at our manufacturing footprint, it has expanded quite significantly just over last few years. Obviously you see we are expanding quickly in Arizona site. We build the first fab focusing on 4nm, which we're going to production next year. And then we are building the second fab there and also we are announced phase three, the third fab there. So we're going to continue to bring the most leading node, advanced node to North America. That's where our largest customer base, right? From 4nm to 3nm down to 2nm or even A16 in the future. So that's very exciting. And the same time, we're expanding our specialty technology in both Japan and here in Europe. Right here in Europe. Japan, the Kumamoto project has gone very well. We're going to production, I believe, second half of this year.

Yeah. So we're going to bring most advanced MCU, embedded non-volatile memory, which is very important for auto industry, here in Europe to the heartland of the Euro zone.

Packaging, we are evaluating options, but the same time I think right now we're working closely with our partner to bring up the capability, manufacturing capability in US. Maybe in the future in other places.

Well, I think yes, AI is becoming, I think, one of the major technology platform where you consume the most advanced silicon. But don't forget mobile. Mobile continue to be a large volume runner and also mobile require most advanced technology. So we are addressing all the needs. We optimize technology for different application, different segments. So our R&D work very closely with different customer, different application. So I think this is something very exciting. We are continue to drive our technology customization to address the future product needs.

Well, aside from me, we want to hear customers. We want to hear what they would need in the future for their product. Foundry business is very, very important to work closely with customer. We want to hear what customers expectation and their product needs, and so we can develop the right technology to address our customer need. Foundry business is a service business. It's very, very important to connect, always stay connected with your customers.

Thank you. Yeah, it's a pleasure, pleasure talking to you.