So look, semiconductors are the backbone of this AI buildout and AI boom we're seeing at the moment. And I have with me the CEO of one of the most important companies in that supply chain, Sassine. Synopsys, what do you guys do?
So our technology is used by our customers' engineering R&D as the tools to tame the complexity of chip design and with the acquisition of ANSYS we provide the engineering solution not only at the silicon, silicon to systems, so envision every intelligent system or product robotics, EVs, etc. We provide the solution for the engineers to be able to design, be it at the physics level or the software level, the product that they're envisioning.
So without your technology, some of the chips in our smartphones, the chips in data centers wouldn't be possible.
There is no chip today that is designed without Synopsys. So we are essential and pervasive in terms of our use at the silicon level.
Great. So that's a good place to start. So you have a great view right now into what is happening when we talk about the infrastructure side of AI. And of course over the past couple of years the key name in everyone's mouth has been Nvidia as kind of the backbone of this buildout around AI training. But actually as the world moves from training to inference, what does that mean for the way you're thinking about infrastructure and the design of that infrastructure?
So chips were initially built to be a general purpose. You build a general purpose chip for a mobile application, for automotive, for various applications of consumer. The most recent wave is the right chip for HPC or high performance compute AI infrastructure and Nvidia has, I want to say, dominated with their chip to be the right general purpose for the AI HPC demand. Then once you go through that first phase, the next phase is typically optimizing for better performance, better energy efficiency, better throughput, etc., etc. And the market has moved to create multiple options for these chips. So you have let's call it the general purpose then you have an ASIC which companies like Broadcom deliver to the ASIC and almost every one of these hyperscalers are building their own architecture, their own chip, which is called the COOT or customer-owned tooling. So there is a different flavor of silicon customization in order to optimize for cost, for energy, etc., etc. And as these models get more powerful, particularly on the frontier, is the infrastructure currently keeping up? Well, the infrastructure is evolving and actually it's evolving rapidly from a training focus to a continuum toward inference efficiency. And in order to get to that inference efficiency, you need to look at the whole stack. So it's evolving. It's different. And that's where you need both customization of the silicon all the way up to the along the stack in order to achieve the right efficiency, performance, cost, etc.
What are some of the biggest innovations happening right now in terms of semiconductor demand? And how much would that — I'm sure everyone's heard about this memory shortage because iPhone prices are going up, PlayStation prices are going up. Much of that is being driven out of the demand of the AI infrastructure buildout. How much are some of these bottlenecks around the industry creating some of the innovations you're about to talk to me about?
You know, the beauty of engineering is when you constrain the problem. And when you have an over-constrained problem, you start looking at the space — you go from a component level to a subsystem to a system in order to optimize and work around these challenges. What we're seeing is, for example, a chip used to be designed in a monolithic way. Now these chips are becoming increasingly heterogeneous chips where the memory, the compute, the networking, they're all put in place as little Lego blocks in an advanced package. And that has been the trend over the last three or four years in order to have optionality of manufacturing, of supply chain, of various sources of, be it memory, etc. So that's the significant trend at an architecture level. How do you architect the chip to provide that flexibility in order to quickly adapt and adopt the new customization requirements?
There's been this sort of new architectures emerging as you're speaking about. You know, on the one side, you've got those that are continuing to use high bandwidth memory, this very advanced type of memory packaged up in stacks. And the others have gone a different route and are using SRAM or some other type of architecture. Is that currently the two waves right now of innovation?
Yeah. There are multiple ways and those are the two out of many different approaches to achieve really one thing: as you're designing the chip, you're designing it for a purpose to achieve the best performance at a low power at a high bandwidth. And you have different architecture tradeoffs along these various vectors that you're optimizing. And this is where the creativity and where you see many companies, be it a startup or well-established companies, trying to position their semiconductor from a chip to a chip in the context of optimized or design in the context of a system.
Well, one of the big focuses right now around the data center is energy consumption, power. And you know how much energy is required for these data centers to run. How much of that energy complex can be solved at the chip and system design level?
Yes. So actually next week we will be at the one-year anniversary of the acquisition of ANSYS. So Synopsys acquired ANSYS for this exact reason, which is how can you co-design electronics with physics? Physics, be it thermal, electromagnetic, fluid, structure, because when you're designing a data center, typically you're designing with a lot of margins and margins equal cost. And the reason you design with margin is complexity and speed. In order to achieve the design, you start building margin. So we're seeing many of the hyperscalers and advanced customers trying to reduce this margin by co-designing across multiple engineering domains. In order to do it, you need to create a digital twin and model an abstraction of the various domains of engineering. So when you think of energy efficiency, it starts from the grid all the way down to the silicon that is running. And where's the optimization opportunity to achieve the best efficiency for the particular — and I'll go back to — application or workload.
And so just run us very quickly through what ANSYS brings to the table.
Yeah. So ANSYS is the leader in what's called multiphysics simulation. So if you're designing anything from a car to a jet engine to a robot, these are at the end of the day physical systems. Designing them with the right cost and time to market requires a lot of simulation. As much as you can simulate and design it digitally before you do a physical prototype is where ANSYS comes in — it's the highest fidelity physics simulation. And as you envision physical AI and you're building these complex products where the brain is the AI model but you still have to translate it into an actual embodied physical system, the need to create a digital twin with a lot of simulation to ensure that that system is going to operate correctly and safely once it's in the wild — it's where ANSYS comes in.
There's another part of this which we've sort of briefly spoken about before you and I but we should unpack a bit more and that is the way you're using AI in the design process of chips. Can you just unpack a little bit more about where you're at in that journey and actually how much of the design is happening right now with the use of AI?
