So, one of the fundamental aspects of this ecosystem we're in is the ability to design the chips that we all use. For those of you who follow the channel regularly, you'll know that I'll cover a variety of companies building the latest and greatest generation chips on leading edge process nodes with the most advanced packaging available. If you've ever spent any time thinking about that, you'll have to understand that the software to design these chips is arguably more complex than the chips themselves. And that's the thing, it's even getting more complex once we add in GPU compute, once we add in machine learning. It turns out that every chip you've bought in the last few years has probably been 50% designed with the help of machine learning. Now, I'm here at Synopsys Converge. This is their big annual conference bringing together all the great parts of Synopsys and their partners to talk about it. You've seen me cover other shows similar to this like TSMC's Open Innovation Platform and Intel Foundry Connect. But one thing is a couple of years ago I interviewed their former CEO Aart de Geus. We had a great conversation on this channel about where EDA is going. I've got a few minutes to speak to new CEO Sassine Ghazi and we've literally both just come off stage.
You guys had me and Sally do a little pre-show warm up the crowd for you.
That was a lot of fun by the way. Yeah. Thank you.
I know, and really enjoyed it. But you also on stage doing all your announcements today. If you want to go find out those announcements, we'll put a bunch of links in the description so you can find out. But what I want to understand from you, Sassine, is given the nature of chip design, it's accelerating, right? We're all seeing it. Companies are now not only producing more products but are producing more volume of products out there. How is your business changing?
So you're right, from complexity and pace, that exponential is getting steeper and steeper. If we go back 15, 20 years ago, we followed Moore's law. Our customers owned their architecture. We provided the software for them to enable the architecture to implement the chip and then they go, the customer themselves, with the foundry partner of their choice and manufacture the chip. About 10-ish years ago or so, the complexity between design and manufacturing became more complex. We played a role in optimizing between design and technology. You look at the chips today with the requirements of AI, the architectures, flavors are rapidly evolving. The complexity of getting to the power, the performance needed is not anymore following Moore's law. So there are different approaches to do it: advanced packaging, multi-die, etc. You need a very sophisticated EDA and you need tremendous number of IP to connect these chips together. We're in a unique position that we lead in the EDA technology and we have the broadest IP portfolio. So from a business point of view, the market, our customers, they've been spending more percentage of their R&D on that automation. So it's been helping Synopsys and the industry quite well given the complexity and the pace of that innovation.
So you're finding that it sounds like time to market is becoming very critical for your customers.
Yeah, because reducing the time to design the chip, it used to be 18 to 24 months. Now you see customers are working on a one-year rhythm to deliver a new silicon. That one-year rhythm, it just means more pressure on everything they do from their workflow, be it the software that we're providing or new techniques in order to shrink the design time.
It's one of the things I brought up this morning, is one of the first companies that integrated chiplets through heterogeneous integration and the difficulty they had at the time doing that because there were very few tools available and these are sort of the tools that your company produces. So as it pertains to 3D chips, multi-stacking, 2.5D, we've seen a number of announcements from leading packaging players going beyond micron level. How have you, it sounds like a really crappy PR question, but how have you embraced the chiplet era?
We enabled it, not only embraced it. Because if you think back to architecture, as you disaggregate from a monolithic to a chiplet, you don't do this manually. Which part of the chip goes on which technology node? Where do you put it in the stack? If you're stacking in 3D, what is the memory role in it? We have the technology called 3DIC Compiler where you start from a spec and architecting that advanced package, chiplet, whatever you want to call it, and do what-if analysis. If I use five nanometer for this versus three, what do I get in terms of power, etc. Then the connectivity between these chips is a whole new other level of complexity. That's where UCIe got born. That's where right now you have the PCIe, the HBM, etc. to connect that system together. So from an opportunity point of view, it's a fantastic opportunity. Where the new things we're seeing is not only semiconductor companies are designing these chips. The hyperscalers themselves are moving from a general purpose to some ASIC that they're needing.
I think Meta just put out a big post this morning about their next generation chips.
Yeah. Almost every one of these hyperscalers, you need to, not because the other two options are not good enough. The time and the customization that you need in order to get the best experience is what's driving those customers to do it.
So when it comes to you, so okay, so you've got your 3DIC Compiler and if we just accept it as a blob at this stage, is that something that you think is born out of customer requirements or that something that you guys already had a project ongoing internally to deliver? Because I'm trying to think timelines here. When do they...
We see things very, very early with the customer. So a 3DIC Compiler actually is a great example. Around 2017 time frame, we could see customers are looking for a different architecture, different package in order to achieve the better performance, the power, etc. to deliver to that future and not only leaning on Moore's law as only the next wave to achieve the leap ahead. So we started exploring developing the technology back then before the first adoption was around three, four years later. Now as the first adoption started coming, then we discovered there's a new challenge which is physics. As the customer started exploring and manufacturing before going to production, they wait a minute, thermal is becoming a key issue. Warpage, the cracking of these die as we're packaging them, physics needed to be integrated and that's where we embarked on truly transforming our company with the acquisition of Ansys.
So on that front, especially with thermals, now I've done some research and I go back and I found a bunch of IBM patents on intra-chip cooling that they did back in the 90s and the 2000s. So I can only imagine that the next stage as we look at multi-stacked chips is you're going to have intra-chip cooling. And you guys are going to have to model that for your customers.
Exactly. Beyond modeling, when you look at the chip, there are certain hot spots on the chip. So you don't want to overdesign the chip.
So do you have visibility over the software that's going to run on that chip? So you can design just right. So you're not overdesigning so it's not too expensive, but at the same time it's not heating up when you run a certain corner case. So if you've got a workload that attacks the ALUs or the memory in this way, can you design for that workload? But you might end up with a workload-specific chip.
Yeah. But otherwise you just overdesign and when you overdesign it's not only expensive and takes time, the chip is not competitive because you're building so much margin between the different functions of the chip. Actually today what we announced, the Multi-Physics Fusion, is how do you bring in that physics models during the design phase. So you take into account the IR, the thermal, the electromagnetic, the mechanical. So you're designing just right. So instead of an overdesign, you're co-designing with it. We introduced that concept, by the way, with the Fusion platform. But 10 years ago, the challenge was less physics. It was how do I close the timing on the chip? How do I close the power on the chip?
Yeah. Especially if you're trying to get timing between multiple chips in the same stack and you know the overheads therein. If you like this content, there are multiple ways to support the channel. You can like and subscribe this video and many thanks for doing so. There's also a Patreon which gives you access to our Discord. There's a merchandise store and a newsletter links in the description. For all of you who do contribute, thank you. You are keeping me well-fed. Does wafer scale present any additional problems?
