Welcome listeners to the second episode of Semi-Doped Podcast. I'm Austin Lyons of Chipstrat and with me is Vik from Vik's Newsletter. We write about semiconductors on Substack and now we have a podcast. Today Vik is going to tell us about five cool things from the IEDM conference and why it matters. So over to you, Vik. What's IEDM?
Hey Austin. Yeah. IEDM, that's short for International Electron Devices Meeting. So this is a conference that I went to in December 2025, and it's a conference that's entirely dedicated to transistors, optics recently, and a whole lot of stuff like about how interconnects are made, everything about transistor devices, memory, all kinds of fancy things like magnetoresistive RAM, ferroelectric RAM, you know, anything you can imagine that's like even five to ten years into the future. Very exciting place.
It's cool. Interesting. So, is it like transistor physics type stuff or are like circuit design folks there?
Yeah. Yeah. Yeah. It's actually transistor design. Okay. So, that's like the key focus of this conference. There's a lot of like chemistry involved and there's like a lot of material science involved. So, this is like the actual core transistor devices that are being made. The circuits version of that would be the Solid State Circuits Conference that's going to be held in February 2026. That's a nice conference to go to. I attended that last year. But this is just core devices.
Gotcha. Cool. And so why should our listeners care? Why are we talking about that today?
Yeah. So all the stuff that we see in transistor land, like you know Intel's 18A or 14A or you know TSMC's newer nodes, all of that starts at conferences like this. And all of what they launch into production eventually starts with technical discussions at research conferences like this. So you have like people from all the major foundries show up to these things and they show the kind of projects they're working on five to eight years into the future. So it's a really good place to go visit so that you get an idea for really what's coming down the pipe, like far out there, you know, and it gives you really good insights into what technology cares about, what people care about, and what it takes to design something that is actually useful in the real world. So it's a research conference, it's highly technical, but the people there are very interesting.
Gotcha. Interesting. So as an engineer it gives you a sense of like what's coming beyond the current set of technologies that you're using and maybe for investor type audience it's a glimpse of what technologies the future might hold which of course they could think about with respect to what companies might be interesting looking five to eight years ahead.
Yeah exactly. So in conferences like this if somebody asks me I always tell them always sign up for like the tutorials or short course sessions because they take you from a reasonably basic state to almost cutting edge in like an hour and a half in a single talk. You know the technical sessions can get quite intense because they give maybe half an hour to you know show their absolute cutting edge thing that they're working on. That's like a little much, you know, for the general audience, unless you're really working on this stuff. It's kind of cool to see, but really the tutorials and short courses are amazing because you can go through the entire history of certain devices just by attending this for one and a half hours a session. And it's usually the first two days before the main conference starts. So even if that can be attended by a more generic audience, it's actually worth it.
Nice. Awesome. That's a good pro tip. I didn't realize that you can go essentially get up to speed and then when you sit in to those talks they might just be right at the cutting edge and you might essentially lose interest after five minutes because they've gone so deep into the weeds that you know you check out but the short course and the tutorials are actually sort of a great place for a lot of people.
Yeah, it is. It is. Yeah.
Nice. Highly recommend it.
Awesome. All right, man. So, what is the first cool thing that you saw at IEDM?
IEDM. Actually I have a precursor to the first cool thing. I have like the 0.5 cool thing. So in one of the before one of the sessions I was just like hanging out and I ran into somebody from SemiAnalysis. So we were chatting and then we met this person who is a very prominent technology person at a very prominent foundry and they asked me not to say who or you know which foundry. So I'm just because they want to leave me out of it. But it was such a fascinating talk because I never imagined that I would attend one of these conferences and like I was saying the people are so interesting who you run into that this person was actually part of a technology pathfinding team at a major foundry. Right? So this person's major role is to find out how to make the transistors that we would use ten years from now. And it was very fascinating to see how they think about this because you know you probably want immediately work you know a transistor that works immediately right like you want all the good properties of this they don't look at it like that they're like they invert the problem on their head so what they do is they're like out of the twenty problems that I will run into in developing this fancy transistor trend ten years from now what are the biggest blockers like there are some of them that are known so they don't even touch that stuff. So when somebody asks for this, you know, very basic almost glaring absence of data on something, they say, "Oh yeah, we know how to solve that problem. So we're not going to look at that at all." You know, so we're going to solve what we think are like absolute blockers where this technology will not proceed unless these problems are solved. So this is the kind of thing they look at and they look at manufacturability at scale from a very very early point in the process of making transistors. So you would think that it's something like we just make this transistor and figure out later whether you can print billions of them. They do not think that way at all. You know they think about manufacturability from the very you know beginning even if it's ten years out. It's very fancy. And it was nice that I got to talk about this kind of stuff for like an hour where everybody else had gone into their sessions and we're listening to the talks in the empty hallways and I've got this, you know, head of this person at this major foundry explaining to me and the guy from SemiAnalysis how transistors work. I'm like why how does this happen? This is ridiculous.
But you know this is this is why Yeah. This is why you go into conferences. You never know what happens. You you don't know what you don't know kind of thing. I love to Yeah. just to go and get access to talk to people and you can learn so much if you can just get face to face with the right people.
Right. Right. Definitely.
Right. Now, now we can go on to the first cool thing I saw because I thought I should just mention that because I'm still kind of stoked by the whole experience.
So, interestingly, you know, in every conference the organizers do one unique thing and when you attend a few conferences you start to see the pattern. They keep some of the most interesting talks towards the last day. And the reason they do this is because they don't want you to leave after the first two days and then go check out the local eateries, right? So they make sure to keep some of the interesting talks. So what I'm going to talk about first is like actually what happened on the last day. So they had a session called Silicon Photonics for Energy Efficient AI. And so I was like, "Oh, I've got to attend this because every major conference now is going to have a significant portion of it dedicated to silicon photonics." So this is an increasing trend that we're going to see going forward. Tells you how important this topic is. But one of those talks was actually from Nvidia and obviously you can imagine if it's from Nvidia then everybody's going to pile into that room. It was packed like people were standing on the aisles and all that and essentially they were just kind of explaining what kind of networking is going to be used and where optics fits in and all that. It was nice but the one big takeaway I had from the whole thing was that for the next generation of the Kyber Rubin Ultra racks that optics is still too expensive for scale up. That was the key takeaway from this. Because they had a slide up there that says like okay if you have like 200 gig lanes and eight of them running a 1.6 interconnect and if that's running let's say 9 W which is kind of reasonable if you think about like a co-packaged optic system because you've done away with the gigantic DSP that you have to deal with in optical transceivers regularly that sucks up you know 20 watts of power all by itself. So now you know you drop from something like 30 watts overall from optical transceivers to just 9 watts or so with co-packaged optics and that's the whole you know allure to co-packaged optics the lower power consumption you're spending about 5 picojoules per bit and so if you translate this to a Rubin Ultra rack it seems that it would take up about 20 kilowatts per rack this was what was on the slide and they also had a dollar value associated with it. Which says that at 5 picojoules per bit and 20 kilowatts the cost to run this would be like $400,000. I calculated that to be about 5 cents per kilowatt hour. I don't know. I don't know exactly how the money part of it was calculated. It was just on the slide. Anyway, I think their point is that even 200 kilowatts is a problem at a rack scale. So, they were like, "No, we want to use copper as much as possible." I mean, we've heard Jensen say this before, too. Copper is where it's at. So, optics is nice. Co-packaged optics is nice. I'm sure we'll get better reach out of it, but people just want to stay with copper as far as they possibly can. So, that's my takeaway. What have you heard about this whole scale up thing?
Nice. Yeah, that's a good takeaway. Well, and it's very timely because a lot of people are asking and I know you've written about it on your newsletter. When will the industry transition to optics for scale up and what's going to be the driving factor? And so I guess that's one of my questions for you in you know you said well wow there's still a lot of power that is consumed there but there's cost was very significant is it what's too prohibitive right now did you get from that talk was it the cost angle or was it the power impact?
I think the key takeaway from what I heard was 5 picojoules per bit isn't good enough because it translates to a lot of power if you look at active electrical cable, we are at about half of that.
Gotcha. Yeah. Well, and that makes a lot of sense because power is the sort of the ultimate constraint, not money, right? So, it feels like if the power was acceptable at this point, but the cost wasn't quite there that some people might jump over that hurdle and not be too concerned about it. But definitely if you can only find so many megawatts of power at your facility and you want to instantiate or install a ton of new Rubin GPUs, it's all about power. So whatever you can do to save as much power as possible so that you can run even more compute that seems like the driving constraint right now.
Yeah. And the other thing I want to add to that is that do we really believe that 200 gigs per lane and 1.6T is not possible with copper because if you look at Marvell's Alaska DSP, you know, it can run 1.6 terabits per second. Of course, I don't know exactly to what reach. They claim it's about like 5 to 7 meters. It should be okay. But then you've also got this other thing like microLEDs that's, you know, maybe useful. We don't know. Nobody's really deployed microLED as an interconnect technology, but it seems like it's lower power and less expensive than going to co-packaged optics right away for even scale up. I want to see what happens with microLEDs for scale up. That's something I want to look into in depth for the newsletter as well. So, it's in my plan to do. But yeah, there are a lot of options before we really have to hit optics as the only way forward and I think people are going to be looking for any and all options before going optics.
Yeah. Yeah, it definitely sounds like at the 1.6T generation that copper is still the way to go. Active electrical cables. And you know, the nice thing is Nvidia is cramming more and more GPUs into a rack. So to scale up, you don't have to reach as far. So even if your copper as the speeds scale up and your reach shrinks, well, guess what? That reach can still reach quite a lot of GPUs. So it definitely makes sense that for scale up, it's still copper for a while. But it will be interesting to see where this inflection point is as we'll continue to track this, you know, and where optics make sense for scale up.
Awesome. Let's go to number two.
Sounds good.
The next thing was about complementary FETs and the progress you know for digital devices in the future and logic. So for anybody who's not familiar with complementary FETs I'll give a quick introduction as to how we kind of got here. You know in the beginning we had planar FETs. This is, you know, back in the 1990s or before that where you could only control the transistor gate from one side. And so the channel was kind of, you know, uncontrolled as it got smaller and smaller. And basically sometime around 2005 the you know the Dennard scaling kind of ended and you know the sub-threshold leakage was too high and transistors were leaking too much current when they were supposed to be off and it just you know didn't work at that point. So the industry transitioned to like FinFETs which means that you know your gate instead of looking like just controlling from one side. It looks like a shark fin where you kind of control it from three sides and that gives better control over the channel and lower leakage as you scale it down to smaller factors. And then today we've kind of gone into the gate-all-around where you can surround it on all four sides and control the channel completely. And that's what you know say 2 nanometer processes and below are going to be gate-all-around. Now the problem with gate-all-around is still you've got an NMOS transistor and a PMOS transistor which is what makes up for CMOS complementary because you've got an N-type and a P-type MOSFET together and you need both together to make all these circuits work. You know they're side by side so that still takes up too much space. You know they're really small transistors but they're side by side. Now complementary FETs is the way of asking what if we took those gate-all-around FETs and put them more on top of each other so that you know we could build skyscrapers instead of you know single-family homes or whatever. And that way we can cram even more transistors into a you know smaller footprint and get even more chips and transistors per unit area. So that's where complementary FETs are supposed to be going. We will likely see complementary FETs come out around the 5 nanometer node or 7A if you want to call it 7A. Don't know at this point it doesn't even make sense to call it like conventional node names anymore. But if you want to compare it to 14A, which is like 14 angstrom, we're looking at a 7 angstrom technology that would kind of use CFETs.
Yeah. We almost should just switch to naming it like CFET version one, CFET version two, right? Like gate-all-around version one, gate-all-around version two, that kind of thing.
Yeah. Yeah. Yeah. So it's far out there. And so the one thing that TSMC has been steadily showing over the years is that in 2023 they showed basic current voltage relationships of a CFET. So which means they show an NMOS on top and a PMOS below. And there are some reasons why I'll mention very shortly why this NMOS is on top. But then they show basic current voltage relationship. So you kind of see like the typical curves you see for an NMOS and PMOS device. This is the basic step. You know, you got to show that the transistor works as a transistor should, you know. So, the next step in 2024, what they did was obviously when you have like an NMOS and a PMOS, literally the first thing you do in digital circuits is you build an inverter out of it. You put an NMOS and a PMOS on top and you hook them up and then you put a zero input, it gives you a one at the output. And this is like literally the first thing you do. So, that's what they did in 2024. And in 2025 actually it was kind of a big jump honestly because what they did was make a ring oscillator. And what a ring oscillator is is you know you take these inverters which has an NMOS below and a PMOS on top hooked up together and you put like 101 of them together. And when you do that what ends up happening is that it basically acts as an oscillator and the outside at the output side you see basically a square wave when the oscillator is started up and usually the oscillating frequency for such a ring oscillator with 101 stages is quite high. So they usually go on the output side and they divide that frequency down so that they can actually measure it with like lab equipment. So the thing is why ring oscillators? So ring oscillators are a perfect measuring vehicle to estimate what the delay is through a transistor or in other words how fast the transistor is. If the delay through the transistor is really small then the oscillation frequency would be much higher and which means the transistor operates much much faster. Right? So that's a ring oscillator is really a fundamental circuit. The moment you build an inverter the next thing people do is put them together make a ring oscillator. So this is the next logical step. It was fancy to see actually. There's a lot of engineering that goes into it. I mean I can't even begin to say how complex something like this is. It requires even new material inventions because you want to isolate the NMOS on top from the PMOS below. So there's an intermediate material that's very important and there's like a lot of innovation in just the material that separates the NMOS from the PMOS. So there's all that kind of stuff. It's kind of insane. And they put interestingly the PMOS down below because apparently when you squeeze the PMOS device by putting an NMOS on top its mobility improves and you know when you strain it somehow it conducts more holes. Okay. So they decided they'll put the PMOS down below and the NMOS on top so you can get better performance out this way. But again this is so far out into the future. Nothing is set in stone. If they find a better reason to put NMOS below they'll do that you know. So it's very very far out actually.
Gotcha. Interesting. So zooming back out. So CFET is sort of the next thing. We went FinFET essentially RibbonFET and CFET's next. And over the last couple years we went from just seeing like hey look we made this and it has the type of IV curve you'd expect to hey check it out. We can make an inverter to now we can make a ring oscillator. So we can make lots of these. We can connect them all together and then we can measure intrinsic properties of the transistor with this oscillator circuit. And then you're highlighting that in doing so there was actually a lot of innovation because we went from having the PMOS and NMOS transistors side by side which takes up a lot of die area to stacking them which lets you shrink the footprint of the transistor or the pair. But it actually required new sort of research and development techniques to actually be able to stack them, to have it work, to be able to probe them. All of that's very promising. So, do you have any expectation of what we might see next year?
That's a good question. No, actually, I have no idea. Because I'm not sure what they're going to do next with this. If you had asked me this last year after I saw the inverter, I would have said ring oscillator.
But maybe we could do more such building blocks around. Maybe we could see some simple other simple circuits. I really can't think of anything. But I'll tell you what, it's going to be a long way before we can see like a GPU built out of this stuff with like billions billions of transistors. It's going to be some time before that happens. So, don't hold your breath on that one. It's going to be a while.
Gotcha. Very early here. Do you expect that they'll stack more of these on top of each other and keep going in that third dimension?
