Hello, this is Nitin Dahad with The Times. I have the privilege here to be at the World Summit AI 2026 in Amsterdam, in the Netherlands. And we had our opening keynote speaker today, Mark Papermaster, CTO of AMD, and I have the privilege of sitting down with him to have a chat about the whole electronics and semiconductor industry. Mark, hello. How are you?
Good. Nitin, great to see you again.
Yes. It's a really fascinating industry at the moment. We seem to be bumping into each other all the time, but also that's because there's so much going on.
And I keep saying to people in all my time in the semiconductor industry, this seems to be the hottest and fastest moving. Don't you think?
I do. You know, we all talk about AI having this promise to bring more productivity, and it does, but it's also speeding the pace in which we're all being able to move at.
Exactly. And I mean, like you and some of your competitors, you're doing pretty well to advance that, I think. And also one of the things I think, and I'm going to talk about this now, which is basically the whole moving up the stack strategy. We've been seeing it for years where you had like the semiconductors and then the reference designs and then, you know, the big solutions. But I think we're seeing that now with companies like yourself and, yeah, like your recent agreement to acquire World Labs. And I know you're like that, it's still, there's stuff going on, your quiet period, but it'd be interesting to talk about that whole shift because, you know, also you integrated ZT Systems and AI silicon makers are no longer just selling chips. And I think, you know, that we know that you're buying deep software, spatial intelligence, rack-level systems engineering. From a CTO's perspective, how far up the stack do you think a pure-play semiconductor architecture company has to go? Are you reaching a point, and I think the answer again is obvious, but it'd be interesting for a discussion, which is: are we reaching a point where designing standalone accelerators without owning the world models, system orchestration, and rack design leaves performance on the table? Long question, but I think it's quite interesting.
It is. So look, I've actually been talking about this topic for years, Nitin, and I've been, I coined this phrase holistic design, meaning you can't just sub-optimize any one component of compute infrastructure and systems. It has to be from the silicon, and when I say the silicon, I mean not just what we do in AMD as chip designers, but the partnership we have with the fabs and right into the silicon supply chain. But then moving up in terms of then how you integrate silicon, how do you connect it, how do you organize, how you put parts of that silicon together, how do you integrate it efficiently, because moving data in a system is actually what consumes most of the power.
But then you can't do it with hardware alone. It has to be hardware-software. So we are committed to open ecosystems, but as you mentioned, we have acquired elements moving up the stack. So we've acquired Xilinx with adaptive compute, we acquired Pensando Systems with networking, and we acquired Silo Labs which helps us optimize and put whole solutions together. And now most recently, the plan and agreement to bring World Labs in, and it's all about that holistic design. So we don't think we need to sacrifice our commitment to an open ecosystem when you look at what we call, and in fact I did mention ZT Systems, which allows us to integrate full rack-level optimization. But again, we do that by creating references. So our software stack, ROCm, that enables AI, open, the reference rack that we do, it's all part of OCP, it's an open standard.
We'll be there next week.
Next week. OCP, in fact, our CEO Lisa Su is giving the opening keynote.
Should be very good. But the fact is that the insatiable need for computing is so high, the need to do that within the limits of the power which is available, power is performance, power is the limiter. So the need to optimize, to attack and deliver those insatiable needs of more computing means that it requires this holistic, encompassing optimization, and that's exactly what we've been on a journey and have the necessary elements to really have leadership optimized compute and AI systems.
And you know, it's interesting because like people like us in the industry with EETimes and many of our competitors, we've been following you in this industry for the whole like four or five decades. And it's quite, I mean, Xilinx you mentioned there, I was one of the early journalists to write about the XC64 back in '87, so it was a fascinating move then. And yeah, like we went from ASICs to FPGAs, and now maybe one of my questions later will be moving, we'll be moving back to ASICs. But it'd be interesting just following up on that last question. So with AI pioneers like Fei-Fei Li joining AMD to shape future chip and systems design, how fundamentally does spatial intelligence and 3D environment simulation change the microarchitecture of your next-gen Instinct accelerators or EPYC processors compared to standard LLM token crunching? And I think that's where you're moving to these custom architectures as well, or hybrid architectures, which is one of our panels today as well.
Well, Nitin, the way that we think about it at AMD is, I'll just take one word that you've heard us say again and again and again: heterogeneity. AMD was a pioneer in heterogeneity. AMD was the first to really combine CPU and GPU. I think it was 2011 when the chip named, code-named Ontario, merged those key compute elements into a single die. First time in the industry at mass production. And so that need for heterogeneity really has done nothing but expand, because what AI is having all of us think about, how we're becoming more productive, and we all use it in different ways. Every industry has different needs. You might need a very interactive, low-latency response. You might need very high throughput. Well, those demand very different architectures. And so what we've done at AMD is created a modular approach. So we were the first to really bring chiplets out in production. So your question with Fei-Fei and the team, we have tremendous flexibility. We also, you know, we have our CPU, GPU, our networking. We acquired Talos, which is a very, very optimized and low-latency inference engine. So we have all of the piece parts. And when you think about world models, physical AI, robotics, AI that's going to be embedded around us in the world in which we live in, that's where AI is moving to. So bringing AMD and World AI together with this planned acquisition is very strategic for us because it will indeed allow that holistic optimization right through the physical AI model.
You got holistic in there again, which is...
You're on message. One of the things I think, when I asked my colleagues at EETimes here, okay, what can I ask Mark, I think one of them asked about chiplets. And yeah, like you were one of the early pioneers of the commercial chiplet trend, but now what we're seeing is massive rack-scale AI systems, compute, memory, networking behaving as a single holistic engine, as you just said. Where is the chiplet paradigm heading next, and are we pushing the limits of packaging, you know, 3D co-packaging, or, you know, what are the biggest bottlenecks? Is it thermal, yield? What's holding back even denser heterogeneous integration? That's a big question, but I think it allows you to explore a little bit in there.
Happy to. Well, you know, when we launched chiplets, and again, first to really commercialize that, it was a necessity. We looked at what we needed to do in AMD, and we were the upstart company, go back over a decade ago. We weren't the trillion-dollar market cap company that we are today. We were the upstart returning ourselves. We set a clear goal of performance leadership across our whole performance portfolio, and we wanted a diverse portfolio. Well, chiplets allow us to create that flexibility to tailor products for server versus PCs versus embedded markets. Different combinations of compute engines, that might be different combinations of CPU engines for the markets that we were serving, with different numbers of chiplets, with a separate control, but the same in GPUs, and in fact, different combinations of CPU and GPU. We've integrated them together in supercomputing applications. So the modularity gave us tremendous flexibility to address broader markets and to really optimize for those markets. It allowed us to handle the difference in technology, because logic circuits aren't scaling at the same rate as the memory circuitry or as the IO interconnect, analog mixed-signal circuitry. And it gave us the flexibility to partition and keep the logic on the latest leading-edge node, but other nodes that weren't scaling as well could be trailing in N minus one and N minus two node. That gave us that advantage, and we were a leader then in CoWoS, to then take all of that, and where it makes sense, CoWoS doesn't make sense everywhere, we still have monolithic chips, but where it makes sense, given the complexity, given the number of transistors, we were a leader in CoWoS. So 2.5D connectivity, and with hybrid bonding, 3D stacked. So we've had for years now 3D stacked memory. Where is it? This trend's going to continue because again, we're limited by power in it, right? And so given that data movement is such a high contributor to the total power, what you're going to see is more and more where we really need that silicon-to-silicon connectivity will continue. CoWoS now is many, many reticles that we're piecing together. So you know that our future modules are quite large, but it's going beyond that. We're actually leveraging technology that you've seen display makers use, and using glass and using panel technology. So I could not be more confident about the future that we, the industry has not run out of new innovations. So we continue to scale, and elements that can be disaggregated have been limited, because sometimes when you disaggregate, meaning separate out, for instance, memory pools or separate out different clusters of computing, we're going to borrow the photonics and optical interconnect that you see clusters being with today.
