Well, hello everyone, it is truly wonderful to be here. Looking back, 40 years ago, at press conferences, growth, and in that time, we saw what became the motherboard and then the PC business, which grew into the server. It was an exciting, nascent, and yet transformative time in Taiwan. And today we see that once again we're back in Taiwan. And in Taiwan, we see this extraordinary growth faster and more than Taiwan. As I joke, you and I can have breakfast, and by lunch Taiwan has produced the prototype, and before dinner we have early production. Nowhere else in the world do ideas move to reality faster, more significantly.
The speed, and has never been this good, right? If you think about the economic growth over the last number of years, it is just extraordinary. It is simply amazing to see how rapidly, as you might think it is kind of clearly true that AI has been good for Taiwan and Taiwan has been good for AI. Clearly, the AI workload has been the driving force that causes the acceleration of the economy of Taiwan, and Taiwan has seen the growth of worldwide AI in industry and statistics here. I just find it overwhelming to think that with 25 million people, Taiwan is now the US's largest trading partner. Think about the significance of that, that you have known these countries that are billions-plus people. Economically, the significance of Taiwan to the tech industry is extraordinary. AI has been good for Taiwan, but Taiwan has been essential to the AI build-out of the world.
When you think about AI, how much AI do you want? You know, and for me, you know my number is, I want 10,000 times more AI. I want you to give that, you think small AI. And efficiency. I want processes to be AI processes. I want manufacturing to become AI-enabled, and I want that to naturally eyes and inners. Language, medical, economic engagement. So I would like 10,000 more AI. So can we give 10,000 times more power to AI? Of course not, right? We're barely able to keep up with the power demands of AI today. The US increased power by 5%. Power for AI could increase that by 10,000. Could we give AI 10,000 times more? Could we build that many more factories? Every one of these answers is of course no. We must make AI at 10,000 times more efficient. Efficiency is added to us.
That is what we do at Playground. We build companies that create a kind of dramatic dislocation because we believe AI is a force of nature, and we are creating the fundamental rebuilding of the tech industry. Incremental improvements—making, you know, a chip 10% better, you know, improving power delivery by, you know, 10%—is irrelevant when I need to accomplish 10,000, right? We need radical new approaches, and that is what we like to do at Playground. That's why we like to come here; that's where it occurs. And for our companies around our company, to get to our companies, and we're excited to have companies that give updates on our conversation. Today we come to announce new company breakthroughs of our companies and to even, for the first time, present some of our stealth companies to the world. We like coming here because this is the place where unique breakthroughs become ideas, but they become realities, and particularly, you will hear from two of them today for new milestones that they've reached.
Lastly, we announced that we're forming a new memory company. Obviously, we see that the memory market has become explosive because AI is a memory-heavy workload. Memory has never been this compelling because how many major new memory architectures have been created over the last 30 years? DRAM, flash, no major new breakthroughs. Incremental improvements? Most certainly, incremental innovations, most absolutely. But in terms of fundamentally rethinking memory, and with that, we're thrilled to be able to present what we think is the company that brings the best of the best of RAM and the best of flash into new physics, into a new device that enables us to deliver a major new breakthrough in memory.
When I used to design chips, package, assembly, and test, I sort of didn't care. It was always that backend stuff that didn't matter, right? We'd figure out how to get testers and how to get them in production; it was maybe 10% of the BOM. Now we think about 2.5D, 3D, and 3.5D, you know, combining multiple materials, multiple devices, etc. Package, assembly, and test is the problem. In AI systems, the rack has become a unit, has become a chip, right? You're seeing this dramatic integration of the technologies, and for that, we're thrilled to present CNS to you today as well and their breakthroughs in package, assembly, and test. So across each of these, we are trying to break the limits to rebuild the architecture in a fundamental way, right across, you know, light, right? You hear from our photonics and optical companies. God said, "Let there be light," and we see, you know, that the photon replaces the electron in so many areas of the computing power, bringing power efficiency at scale. And finally, fundamental new computer architectures, and against those companies that truly Peter and others have you working with some of the brightest innovators and founders to have one of the most bright and impactful boards, you know, the gentlemen joining me in this, whether you kinds. So we had a good run with computation.
80 years ago we invented transistors, 60 years ago we invented the integrated circuit, and 40 years ago we developed the algorithms behind the AI revolution that we're experiencing today. But 20 years ago those transistors stopped getting faster, 10 years ago they stopped getting cheaper, and now we're faced with real limitations on energy, production, and the scale of building giant data centers. What does that mean? Does it mean that we're out of ideas? Are we running out of Moore's Law? Are we running out of innovation? Or are we at the threshold of an endless frontier of new ideas, physics, and engineering that can lead to an extraordinary explosion in the amount and kind of computation available to create wealth and opportunity and reduce human suffering? And I would argue we are just scratching the surface, and some examples of that are things like this machine, right? Most complicated machine on Earth. This is an ASML high-NA lithography system, an extraordinary machine that is limited by how much extreme ultraviolet light it can produce. Uh, and this machine is actually capable of using a lot more photons than it can actually make, and so enter XL, who is using the most powerful lasers to dramatically change the amount of light available for semiconductor manufacturers. It does so at 20x the efficiency of today's systems, so dramatically reducing power requirements, but also making transistors cheaper again and changing the economics of a that we no longer have to choose between density and speed for memory, right? So much of the AI depends on this HBM memory; we have degrees of freedom to push that technology into new realms.
We also have new ways of packaging these increasingly sophisticated systems at scale, uh, and we're no longer constrained by a single process, uh, in a single chip. We are seeing a huge shift from electrons to photons for if you need hundreds of terabits, uh, of connectivity. Co-packaged optics from AGI is really the only way of doing that, uh, that the demands of networking, uh, in AI change what the dynamics and access patterns of networks look like, and technologies like, uh, will give us new degrees of freedom. Seen together, we also have dramatically different ways of interconnecting, uh, and getting photons at electron prices. And the rise of micro-CXL, uh, from companies like Picadel, is going to reshape, uh, the way we wire, the way we replace, uh, with the scale of interconnects, uh, and with, uh, the advent of very, very dense optical interconnects, so that degree of freedom is ahead of us as well.
Uh, we also know how to make more power. Nuclear energy still remains the safest way of generating firm power, uh, and our company Aleph Energy can within the footprint of the US, uh, nuclear add 10 GWs, or also simply by operating existing reactors, and then over 100 GWs by adding new units to existing reactor sites. So without changing the fenceline, without new fuels, without new physics, uh, we can add 100 GWs or more to the US. Uh, and I'm excited about the prospect of, uh, nuclear energy filling some of the gaps that exist today. But speaking of power, we also have a lot to do with getting the power into the computation. Uh, and so technologies like vertical bonding from Vertical Semiconductor greatly reduces the losses in conversion throughout the data center. Uh, and PowerLaps has a revolutionary power chiplet, uh, that allows the losses, uh, delivered from the substrate into the computation to be greatly reduced. So these are new materials, new systems that can greatly eliminate much of the heat that we deal with.
We also have degrees of freedom in architecture to be able to do near-memory compute or in-memory compute to be able to stack RAM on top of logic, and companies like Matrix are showing the way as to how these architectural shifts can improve the performance of inference by multiples, in some cases orders of magnitude. But there are other architectural shifts that are happening. This is the Esperanto supercomputer. It's the most recent supercomputer built there. This was built on an architecture from silicon that doesn't use CPUs or GPUs. It runs existing software, including software that was written in the 60s. Uh, but this technology shows a path forward that means we're not locked into executing standard instructions. We can do things very differently. They produce the world's most sophisticated RISC-V CPUs.
One thing we don't talk about with AI is that nobody really knows how much AI is going to increase the need for compute work. Uh, and we think that having extraordinary new opportunities in different architectures, but more importantly, new kinds of CPUs, uh, is going to be an important factor in the future. Tech science fiction: it can reduce the footprint of a data center, both in terms of size and power, by a factor of 100. It's cryogenic logic; we're going to be hearing about that from Snow. Uh, but this is an example of a degree of freedom that is not for anybody, but that physics allows. But this, speaking of physics, is a million-qubit machine being constructed. Uh, in Chicago, this machine is 10,000 times the size of state-of-the-art. In building a quantum computer, you're redefining the underlying technology for classical computation as well in terms of, uh, in terms of optical interconnects, in terms of optical switching. And that quantum computing also leads us to fundamental new scientific discoveries in science and engineering. We know things today because of algorithms that are running on quantum computers that reveal the nature of nature in new ways, which will lead to new capability in delivering computation, and that includes This is a new result that will be public tomorrow, that allows us to print qubits onto photonics.
We embody our AI in robots. This company is J-Robot. Robotics will be the first human-ID company, and this company, Robustas, a Foxconn-manufactured robot, doubles the productivity. But we know how to talk to AI in a way that is indistinguishable from, we know that in the future we will be able to speak to AI and they will be able to speak to us by simply thinking about it, and that we are scratching the surface with how we realize AI and what it's called, that our brains don't do matrix multiplications. Unconventional AI is developing wild new ways of doing computations that are thousands of times more efficient than what we do with multipliers in. The human impact of AI is, I think, represented best by a company like XLS, which uses AI to tackle most difficult diseases and to be able to do surgeries that would be impossible without the help of AI. And so, in summary, I think we are right at the beginning of something, not right at the end, that there is an endless frontier of physical AI, and Taiwan is where computation becomes physical. And so we are grateful to be here and we look forward to partnership in realizing this emerging world. Thank you very much.
>> Thank you also for the target. Please return to your. Thank you very much, Peter and P, for bringing us some innovative development directions for next-generation computing, and also showing us some of the key technological breakthroughs from the portfolio companies. Next, we will gain a deeper understanding of the latest key technological breakthroughs from the platform's portfolio companies. First up is AR Labs, which is dedicated to developing new types of crystal technology with high density and high speed, which can bring infinite possibilities to AI computing. Now, let's welcome Data, the co-founder of AR Labs, to the stage to share with us. Please join me in welcoming Data. To come up to the stage. Please give him a round of applause.
Thank you so much to be here. And today is a big day for our company. The announcement, the launch of AR Labs. And thank you, and other. Day. So, this is a Japanese word, and "aru" literally means the flow. "Igital" means the flow of life, how to get the balance of life. And in our case, we were inspired by that name. Because for our case, it's about the flow of data. And as mentioned, the flow of data is the most important thing today as we build massive. AI, so. New AI memory, so. AI inference, so. All those fluid, responsive.
Just to introduce myself. The CEO. Labs, when Labs, also a professor in computer engineering. My career, actually at, when there we go, when I was there and, and I worked on multiple generations of logic transistor technology. So I'm actually coming from the logic transistor world and moving into the memory world. My co-founder, My. And is an expert on circuit and system design. So together, we form a. Team that pretty much covers the stack all the way from silicon to the systems. We also are very lucky to have two very famous folks in the semiconductor industry as advisers. We have, expert of time, developer of memory technology, and, known memory expert from Stanford University.
All right, so we already heard about, when I first started looking at this problem in AI, I thought training was the hard part, right? And that inference would be easy. Turns out that's not the case. We have officially entered into this era of AI entrance. And as the context window increases, the number of tokens that we are dealing with is just growing exponentially. And this is what is driving this hardware disaggregation. And let me just quickly tell you why this is a problem that is going to continue to exponentially increase in number. When you actually go to inference, it has two phases. One is the prefill, you just bring in the tokens all at once and you compute on all those tokens simultaneously, parallel, very compute-intensive. But when you get to the decode phase, when you actually push out those tokens, that's an autoregressive operation. It means you got to push out one token at a time, and there is a lot of data movement that's happening with this, with each and every token. You can't, you have to process in the computing cache and the feedforward network part before you can process the next token, so that's creating this workload bottleneck. And the way the industry today is handling this thing is going to this extreme measure of creating a different rack for inference, one just for attention and another for the FF, the feedforward network, so that's just increasing the footprint of our data center. Consuming. The server.
Trade-off between capacity and latency. And we are trying to solve this problem with the new memory technology which can bridge this gap. Density with speed and merge them. So here is the new technology, and if you focus on the center, we are showing the speed versus density. So the extreme of speed is SRAM, the extreme of density is DRAM, and our AR technology is in green. The first generation is related to keeping that balance without having the speed of DRAM as well as the density of DRAM, that's the first generation of RAM with 5x density than SRAM and a similar speed as SRAM, and then we go to subsequent generations.
So to give you a brief idea how this technology looks, it is taking. Oxide semiconductor-based transistors. It's a read and write transistor, it's a pure transistor-based memory. So it's a separate read and write so it's fast and it's stackable in a monolithic sense. It does not require lithography steps to be repeated and, it doesn't require EUV at least for the first generations of the chips, and it's fully compatible with the silicon-based foundry. So the most important thing is, it's thermally resilient because of the wide bandgap that these semiconductors provide. So it can be stacked directly on top of the logic chip and provide that extremely high bandwidth and low latency at the same time, and also lower energy per bit. So again, as I said, today is a big day for us with the launch of the company. This is our first year, and we are just closing the pre-round, and in the next year, we are going into a fab corner selection to bring this technology out of the lab and into a 300mm facility. So Taiwan is obviously the best place to do that, and after that, we will go into more prototyping of samples and then sampling those samples in subsequent years with that. Thank you very much for your attention and I look forward to interaction.
After understanding memory, next we will delve into the latest developments in advanced packaging. Walking onto the stage, let's welcome co-founder Winson to share with us. Co-founder, thank you.
All right, good morning everyone. Uh, my name is Ben Wilkins. I'm the CTO and one of the co-founders. Centa is building a new scale to fabricate high-resolution interconnects for advanced packaging. Now, the problem that we face is that compute density has had an enormous increase in the last few decades, almost 5 orders of magnitude, and this has been powered by innovations and fabrication processes on the front end. For example, EUV. On the backend, we have to keep up. The interconnect density bandwidth metric has only increased by a factor of 100, so this is an enormous gap, and it is a gap that is continuing to widen over time. What we need on the backend is a new innovation of the process fabrication to be able to continue to increase that main intensity to bridge this gap and avoid having a performance gap in the integration. It's not just resolution and bandwidth density; packaging phases are a combined problem to deliver high yields of a larger and growing area for the package sizes. This is also driving this need to go to panel-level processing and still be compatible with these resolutions and yields, and we need a productivity increase to supply the growing number and total area of these packaging sizes.
So we have developed a new fabrication process to try and solve this problem, and it's called Localized Electrochemical Manufacturing. This is a completely new process that combines patterning and deposition into a single co-optimized process. And by combining those two methods together, we're able to bypass some of the manufacturing challenges that the existing processes had. So I'm just going to explain this with an example of actually our patterned electrode. So we use something called a stamp electrode to combine the pattern onto the electrode. So the deposition process is selected. So eventually how our method works is we load material into a stamp into this pattern. We then place these stamps onto a substrate with a small amount of electrolyte. And during the deposition of this process, the material stays inside the dielectric features. And what this gives is independence and a great level of control. And with this additional control, we're able to improve the resolution, improve the uniformity, and fabricate structures that are otherwise very difficult to make, giving packaging designers more design freedom and more performance.
Now you can see this process in action with our most recent tool, and so therefore, the first time we're demonstrating, a scale deposition, with stamps having been placed on the substrate, electrolyte being placed in between the stamp and the substrate, deposition, and then removal of the stamp to reveal the pattern below, and in this example, you can see 5-micron test structures being fabricated in a single process. Now what Centa has to announce today is that not only have we done this on wafers for the first time, we have been able to use this method to fabricate entire layers on wafers, and the next step for us is going to be doing this on panels and then also panel-size substrates as well. This is a method that is intrinsically compatible with different substrates, does not need to be round; the process is essentially stack-based instead.
We also have the resolution to be able to continue scaling density, so we've demonstrated 1-micron resolution, we have also demonstrated sub-micron resolution; we have patterning examples down to 50nm deep sub-micron; we have a lot of headroom to continue pushing. And we've designed this process from day one to be a drop-in tool replacement. So this is a more efficient process with fewer steps. So the total number of tools in the fab space required to deliver not only the same capability but improved capability in terms of resolution performance is less, and existing lines can be upgraded with this tool.
And so what does this mean in terms of packaging performance? If we combine the high-resolution deposition capability with large area and the improved productivity, this is the recipe to be able to continue to improve chip-to-chip electrical bandwidth and the total on-package bandwidth, a 10x beyond what the existing roadmap is. If we look out to the 2030s, looking at panel-sized devices with sub-micron connections, electrical connections of multiple layers between these chips. We are now looking at 10 to hundreds of petabits per second of total bandwidth, which is a direct proportional increase in inference speed and effectively cost. So, to summarise, there are two dimensions that the industry is looking to progress packaging. One is bandwidth density, one is area, and CENTCOM technology has been purpose-built to pursue. Thank you very much.
For the wonderful sharing, and next, we would like to invite Ayar Labs to share with us the latest technological developments in silicon photonics. Please join me in welcoming the CEO to this stage, please.
Hello everyone. Thank you for coming. It's great to be here in Taiwan. You know, I've been here almost every month over the last couple of years. So, it's great to be here and see friends, colleagues, and all of our partners. I'll talk a little bit about what Ayar Labs is doing and give you an introduction to the company. At this point, we are more than a 10-year-old startup, so I think of us as a late-stage startup. We've raised a little bit more than a billion in capital to date. Our founding story came out of some of the academic institutions in the US: MIT, Berkeley, University of Colorado. And we've worked very deeply with our partners across the ecosystem to build what is becoming a new generation of optical connectivity and electronic-photonic integration at large scale. So, we have great financial investors; Playground here has been one of our earliest and most supportive financial investors. And we've spent a lot of time building our strategic partnerships through equity investments and collaborative development activities. So, TSMC, start with the ones in Taiwan, TSMC, MediaTek. We view this as solving a huge problem across the whole ecosystem stack, and we've had to partner deeply with these companies to work on this. We're focused on bringing this optical connectivity straight into AI GPU or AI accelerator kinds of integrations. And to do that, we also worked closely with our partners AMD, Nvidia, and Intel. So, I was at this event last year and said that we were establishing an office here in Taiwan, and we got that entity established. We're investing aggressively in establishing the office space. I've got pictures here of the
office. This is our office down in Hsinchu, and the construction on that office just recently completed in the last couple of months. We'll be having a grand opening probably early next year. So, I'll look forward to inviting a number of you to come visit us at that opening. And we're also ramping up our team here in Taiwan. We've got about 10 people here right now, and we're going to be growing that over the next one to two years to really work deeply with our manufacturing partners and our ecosystem partners here throughout Taiwan.
Now, what are we doing? Well, the previous speakers actually touched on it multiple times, but one of the problems with the big models happening in these large-scale AI systems is trying to scale the bandwidth in data movement between different components in a rack-scale AI system. So today, the core AI network that connects these AI accelerators and GPUs together is bound to a single rack. And the reason it's bound to a single rack is because all of them are connected together electrically. So there are copper wires, copper cables that connect these GPUs and accelerators together. And that's where one of the biggest challenges comes in when trying to scale the number of GPUs and accelerators connected together.
Now, why do you want to scale the number of accelerators? The short story is that, if you can spread the AI workload across a larger number of nodes, you can scale system computation and system memory more elegantly with how the workload is running. So, the AI workload that sits on top of this economics and performance ends up depending on how you can connect all these different pieces together in a system.
Now, electrically connected, you're bound to a single rack. What we want to do is bring this new generation of high-performance, densely integrated, mass-scale manufactured electronic solutions so that we can break that electrical bottleneck and transition from the electrical connections that you see today into the optical connections that we want to go into over the next couple of years and drive this improvement in rack-scale performance. So rather than being bound by a single rack, you can spread the AI workload across and scale that connectivity gracefully.
So I mentioned this already, but [the previous speaker] did a great job setting the stage. We ourselves are helping bring an innovative new scale technology into high-volume semiconductor manufacturing. And to do that, Taiwan is the center of the universe in terms of how you start to manufacture and deliver these things at scale. And this is just a few of our partners who we work with here in Taiwan, very closely. Everything from the ASIC design partnership, MediaTek, GUC, of course anchored by TSMC's role and position in this ecosystem. We also work closely with the OSATs who are forming the backend of the TSMC wafer fab, and all the way out to someone like Wistron who is a strategic investor in Ayar Labs. Because we did the thought experiment all the way out through the chassis and rack-scale infrastructure, and it took work to solve problems across this entire stack to really get things integrated in a high-volume manufacturable way.
We had a great demo at Computex, I think probably some people came by earlier this year at that demo, where we showcased more detail on what we're doing with our partner Wistron in the chassis designs and all the components, and in supply chain partnerships and ecosystems that are going into that. And also, we announced that we are joining the OCP foundation to help bring this innovation into a number of different fabric solutions so that we can really break this.
Here's a zoom-in of what that looks like. We have some of this hardware over here at our table if you want to stop by and see it later, but this is what the chassis looks like. We want to integrate optically connected GPUs, accelerator processors, as well as, you can imagine, this connected into memory and so-called scale-up switches where that AI network [runs]. Thank you.
Next, we would like to invite [Company] to share with us innovative power management technology and how to solve the power supply problems of the current era. Please join me in welcoming the founder of Power [Name] to the stage. Thank you.
It's great to be here. So today, I will introduce what we are doing and what's coming next. So, targeting the last stage of power from the datacenter, you know, right to the last stage, the stage powering the GPU computer and also feeding thousands of watts of power into a single SoC. So we highlight here that all these today's components, all these are point-of-load, multi-phase modules, controllers... surrounded by the GPU. That's actually the... so basically, today's natural part.
So what's the problem of today? As computer power increases, with a single chip from 700 watts to 3000 watts, the overhead to deliver power to the GPU, CPU, is actually more than the computing itself. So you can say only 5% increase of compute power, but there is 5x increase of the power overhead. That's actually lost in the last stage of power. So what's the problem of this power, lateral power delivery? Basically it is too big, too slow, and too far away to fundamentally solve this problem.
So we have to really integrate the last-stage point-of-load. So what we do in Power [Company], we actually build this monolithic chip. We integrate everything into a single IC. So we have controller circuits, power circuits, FETs, and also inductors. Highlighting that the height of this single silicon is only 260 micrometers. So that kind of small form factor really enables this technique to be integrated inside the GPU package and very close to the [load].
So at the point-of-load, we can deliver 200x faster voltage regulation speed and more than 400x power density. So basically, in the world, it's the first time we were showcasing the in-package power, in the package to power the AI chips. So this is the first time.
So to summarize, the monolithic part is a reality. We, that is, bringing that into life, into the field, and for the future, the point-of-load has to be [integrated]. And I believe, we believe, that this is the solution to become the de facto power point-of-load solution for AI. Thank you.
Thank you for the presentation. Thank you, and please return to... Thank you very much for the wonderful sharing. Next up is [Company] to help us understand optical interconnect solutions that can meet the growing transmission needs of AI data centers. Please join me in welcoming the CEO to the stage. Please give him a [round of applause]. Back when his first trip to Taiwan was, I think, 40 years ago.
My first trip to Taiwan was 65 years ago when my mom — actually, more accurately, when my mom gave birth to me. I'm always going to be back to Taiwan. I always feel like it's coming home, and so you know, Playground has been an excellent partner as we build up this type of company, optical connectivity. I heard from so many of their portfolio companies, and it's just an exciting time, both in Silicon Valley, of course, where we're all from, but also for the ecosystem in Taiwan. So I'll talk a little bit more about that today.
All right. Some background a little bit: connectivity here all the time. But what's happening is, for 100 years or so, we had person-to-person communication. So, think of those of us who are old enough, we used to actually have telephones on the wall and we would, you know, answer, etc. Then that moved to cell phones about 30 years ago. So those person-to-person calls... 30 years ago came the beginning of the mobile internet, computers looking for to eat, right? Last week I had to find out how to get there to get an Uber. That's a person-to-Uber type of communication, so that's still quite slow, right? Because if a millisecond delay happens, I don't notice.
Chip communication, everything, right? Pixels have been around for 30 years. We've connected all the data centers that are more person-to-chip, but now chip-to-chip, with hyper-scale AI, it's really sensitive, errors are really sensitive to latency, and as pointed out, power is also very, very sensitive as we build these very hyper-scale systems. So what are we doing about that? And what are all these portfolio companies talking about today? It's one of the things.
Two years ago, when we started, I was invited to many talks around the world, and one of the reasons was everybody thought pixels were over, right? 100G was the limit. Pixels are dead. The future is something else, right? So I had to go and travel the world and be the pixel evangelist, etc. But something happened. During that time, about six months ago, everybody came back to pixels, right? So a lot of people ask me: 'What do you think about Coherent and Lumentum, Marvell, Ciena?' Everyone is talking about micro-pixels all of a sudden, and my answer to that is, 'I love it, right?' I can save my mileage. I don't have to travel the world talking about it everywhere; now we can basically start working every day to make it a reality. So we're working very closely with [Company Name].
Over 10 years, it has been billions. If you have it in your pocket, you have one of ours inside for Face ID. And so with that technology, we're getting ready to ramp micro-pixels. We have already demonstrated 200G at 50G. For us, it's much easier. The problem is the speed for the pixel; now it's changed the packaging, right? So now you have more 'slow and wide,' so that's really where the difficulty is and where the advancements have to happen, right?
So why do all this? Power is really key, right? So we're trying to remove things like digital signal processing chips, which take power, latency, all the things I mentioned, even the, right? The serializer, deserializer electrical signals within a chip are running at 32 gigabit, 50 gigabit, but in order to save the number of I/O channels coming out, they want to slow that... sorry, they want to aggregate that up to 200G, 400G in order to reduce the number of necessary components. But what that does cause is very, very high bandwidth requirements at 200G, 400G. The noise, the signal, everything has to be cleaned up at the other end, so DSPs, all signal processing chips are required, more power, etc.
By slowing it down, slow down the data so all the chips understand each other much better. Right now, I don't need someone to kind of clean up the noise in between; I can get rid of the DSP, all that power goes away. So that's why this 'slow and wide' movement is beginning to happen, mainly driven because of power.
So let me move through. So we basically are leveraging 30 years of packaging here in Taiwan. Multiple partners we're working with, many of them unannounced, so you will hear about them in the near future. But we are working very closely with [partner] right now to build. We've demonstrated the near-package optics, we've done 50G and it's all produced already. Also 100G we're doing, and then we recently announced back in June the 200G pixel as well. So we can do all the different flavors from slow and wide up to 64, all the 100G that's shipping today, and active optical cables, and of course the fast and narrow 200G coming in the next six months or so as well.
So the funny thing is, when everybody moves to micro-pixels, they have this hexagonal plan, and then one of the engineers in our team goes, 'Hey, our logo looks just like the hexagonal pixel that they're planning,' so we believe that we dominate the micro-pixel. We love the competition. We love that larger companies are coming in, and we believe the future is micro-pixel. Thank you.
