【AI翻譯字幕】直播／前Intel執行長季辛格訪台　大談AI與次世代運算｜20261027

[applause] Thank you, Pat, for the kind words. So, we've had a good run with computation, right? 80 years ago, we invented transistors. 60 years ago, we invented integrated circuits. And 40 years ago, we developed the algorithms behind the AI boom that we're experiencing today. But 20 years ago, those transistors stopped getting faster. 10 years ago, they stopped getting cheaper. And now we're faced with real limitations on energy and production and scale. We're building giant data centers. What does that mean? Does it mean that we're out of ideas? Are we running out of Moore's law? Are we running out of innovation? Or are we at the threshold of an endless frontier of new ideas in physics and engineering that can lead to an extraordinary explosion in the amount and kind of computation available to create wealth and opportunity and reduce human suffering? And I would argue we are just scratching the surface.

And some examples of that are things like this machine, right? Perhaps the most complicated machine on Earth. This is an ASML high lithography system. An extraordinary machine that is limited by how much extreme ultraviolet light it can produce. And this machine is actually capable of using a lot more photons than it can actually make. And so enter Xite who is using the world's most powerful lasers to dramatically change the amount of light available for semiconductor manufacturers. It does so at 20x the efficiency of today's systems. So dramatically reducing power requirements, but also making transistors cheaper again and changing the economics of a fab.

But we no longer have to choose between density and speed for memory, right? So much of the AI movement depends on this HBM memory. We have degrees of freedom to push that technology into new regimes. We also have new ways of packaging these increasingly sophisticated systems at scale, and that we're no longer constrained by a single process in a single fab.

We are seeing a huge shift from electrons to photons for interconnects. If you need hundreds of terabits of connectivity, co-packaged optics from ILabs is really the only way of doing that. That the demands of networking in AI change what the dynamics and access patterns of networks look like and technologies like Bellas will give us new degrees of freedom as to how we wire these systems together.

We also have dramatically different ways of replacing copper and getting photons at electron prices. And the rise of micro pixels from companies like Pikachu is going to reshape the way we wire, the way we replace copper with the scalar interconnects and with the advent of very, very dense active optical cables. So that degree of freedom is ahead of us as well. We also know how to make global power that nuclear energy still remains the safest way of generating firm power. And our company Alberta Energy can within the footprint of the US nuclear grid add 10 GW or so simply by operating existing reactors and then over 100 gigawatts adding new units to existing reactor sites. So without changing a fence line, without new fuels, without new physics, we can add 100 gigawatt or more to the US grid. And I'm excited about the prospect of nuclear energy filling some of the gap that exists today.

But speaking of power, we also lose a lot of it getting the power into the computation. And so technologies like vertical GaN from Vertical Semiconductor greatly reduces the losses in conversion throughout the data center. And Power Lattice has a revolutionary power chiplet that allows the losses delivered from the substrate into the computation to be greatly reduced. So these are new materials, new systems, but this can greatly eliminate much of the loss in delivery within the data center. We also have degrees of freedom in architecture to be able to do near-memory compute or in-memory compute to be able to stack RAM on top of logic. And companies like Dmatrix are showing the way as to how these architectural shifts can improve the performance of inference by multiples, in some cases orders of magnitude.

But there are other architectural shifts that are happening. This is the Spectra supercomputer at Sandia National Labs. It's the most recent supercomputer built there. This was built on an architecture from Mexilicon that doesn't use CPUs or GPUs. It runs existing software including software that was written in the 60s. But this technology shows a path forward that means we're not locked into executing instructions. We can do things very differently than x86. They also produce the world's most sophisticated RISC-V CPUs. One thing we don't talk about with AI is that nobody really knows how much agentic AI is going to increase the need for CPU workloads. And we think that having extraordinary new opportunities in different architectures but more importantly new kinds of CPUs is going to be an important factor in the future.

This technology sounds like science fiction. It can reduce the footprint of a data center both in terms of size and power by a factor of 100. It's cryogenic logic. We're going to be hearing about that from Snowcap. But this is an example of a degree of freedom that is not on anybody's radar but that physics allows. But this, speaking of physics, is a million-qubit quantum machine being constructed in Chicago. This machine is 10,000 times the size of state-of-the-art. In building a quantum computer, you are redefining the underlying technology for all classical computation as well in terms of optical interconnects, in terms of optical switching, and that quantum computing also leads us to fundamental new scientific discoveries in science and engineering.

We know things today because of algorithms that are running on quantum computers that reveal the quantum nature of nature in new ways which will lead to new capability in delivering computation and that includes molecular qubits. This is a new result we will be public tomorrow that allows us to print qubits onto photonic chips. We embody our AIs in robots. This company is Julie Robotics, will be the first humanoid public company. And this company, this company Robust AI as a Foxconn manufactured robot doubles the productivity of workers.

That we know how to talk to AIs in a way that is indistinguishable from telepathy. We know that in the future we will be able to speak to AIs and they will be able to speak to us simply by thinking about it and that we are scratching the surface with how we realize AI and what it's for, that our brains don't do matrix multiplications. Unconventional AI is developing wild new ways of doing computations that are thousands of times more efficient than what we do with multipliers and GPUs.

And that the human impact of AI is, I think, represented best by a company like Exile Labs who uses AI to tackle our most difficult diseases and to be able to do surgeries that would be impossible without the advent of AI. And so in summary, I think we are right at the beginning of something, not right at the end, that there is an endless frontier of physical AI and Taiwan is where computation becomes physical and so we are grateful to be here and we look forward to your partnership in realizing this emerging world. Thank you very much.

>> Thank you. Thank you so much. Glad to be in Taipei and today is a big day for the company. Today is the announcement of the launch of Nagari Labs and thank you Peter, thank you Pat, Austin, Daniel and many other members of Playground who has made this day happen. So Nagari, this is a Japanese word and nagari literally means the flow and figuratively it also means the flow of life, how to get the balance in life. And in our case we were inspired by that name, Nagari, because for our case it's about flow of data. And as Pat mentioned, flow of data is the most important thing today as we build these massive computing systems for the era of AI. So Nagari Labs is about building a completely new AI memory technology that keeps this AI inference and agentic world all the way smooth, fluidic, responsive.

Just to introduce myself, I am Suman Datta. I am the co-founder and the interim CEO of Nagari Labs. When I'm not working on Nagari Labs, I also am a professor in electrical and computer engineering at Georgia Tech. I started my career actually at Intel when Pat was there and I worked on multiple generations of logic transistor technology. So I'm actually coming from the logic transistor world and moving into the memory world. My co-founder is Professor Shivaji, he's my colleague, see him somewhere over there. I see Shivaji somewhere in the audience and Shivaji is an expert on circuits and system design. So together we form a complementary team that pretty much covers the stack all the way from atoms to the systems.

We also are very lucky to have two very famous folks in the semiconductor industry as advisers. We have Dr. Sanjay Natarajan who spent quite a bit of time at Intel developing many generations of logic technology and Professor Philip Wong who is a well-known memory expert from Stanford University.

All right. So we already heard about when I first started looking at this problem in AI, I thought training is the hard part, right? And inference would be the easy part. Turns out that's not the case. We have officially entered into this era of agentic inference and as the context window increases, the number of tokens that we are dealing with is just growing exponentially and this is what is driving this hardware disaggregation. And let me just quickly tell you why this is a problem that is going to continue to exponentially increase. Number one, when you actually go through inference, it has two phases.

One is the prefill. You just bring in the tokens all at once and you compute on all those tokens simultaneously in parallel. It's very compute intensive. But when you get to the decode phase where you actually push out those tokens, that's an autoregressive operation. It means you're going to push out one token at a time and there's a lot of data movement that's happening with each and every token. You can't, you have to actually process it in terms of computing the attention cache and the feed forward network part before you can process the next token. So that's creating this workload bottleneck and the way the industry today is handling this thing is going to this extreme measure of creating a different rack, inference racks, one just for attention and another attention rack, another rack just for the FFN or the feed forward network. So that's just increasing the footprint of our data center. Obviously that is adding to the end-to-end latency and the energy consumption. That's how we are handling this problem.

And part of the issue for that is because of the SRAM versus DRAM tradeoff between capacity and latency. And that's exactly what we're trying to solve this problem with the new memory technology which can bridge this gap, give you the DRAM density with SRAM speed and merge the two. So here's the new technology and if you focus on the center of the plot we're showing the speed versus bit density. So at the extreme speed is SRAM, at the extreme end of bit density is DRAM and our Nagari technology shown in green, the first generation is related to keeping that balance without having the speed of SRAM as well as the density of DRAM. That's the first generation of DRAM with five x density than SRAM and similar speed as SRAM and then we go to subsequent generations.

So to give you a brief idea of how this technology looks like, it is taking oxide semiconductor based transistors, it's a read and a write transistor. It's a pure transistor based memory. So it's at a separate read and a write port. It's fast and it's stackable in a monolithic sense. It does not require lithography steps to be repeated every day. It doesn't require EUV at least for the first generations of the chips and it's fully compatible with the silicon CMOS foundry. So the most important thing is it's thermally resilient because of the wide band gap that these semiconductors provide. So it can be stackable directly on top of the logic chip that provide that extremely high bandwidth and low latency at the same time and also lower energy per bit.

So again as I said today is a big day for us with the launch of the company. This is our first year and we're just closing the pre-round with Playground and in the next year we are going into a fab partner selection to bring this technology out of the lab and into a 300 mm facility. So Taiwan is obviously the best place to do that and after that we're going to go into bigger, more prototyping of samples and then sampling those samples in subsequent years. With that, thank you very much for your attention and I look forward to interacting with you.

All right. Well, good morning everyone. My name is Ben Wilkins. I'm the CTO and one of the co-founders at Sienna. Sienna is building a new scalable way to fabricate high resolution interconnects for advanced packaging.

Now the problem that we face is that compute density has had an enormous increase in the last few decades, almost five orders of magnitude, and this has been powered by innovations in fabrication process on the front end, for example EUV lithography, but on the back end we have not been able to keep up. The interconnect density, the interconnect bandwidth metric has only increased by a factor of 100. So this is an enormous gap and it's a gap that's continuing to widen. What we need on the back end is a new innovation in the process and the fabrication to be able to continue to increase that bandwidth density to bridge this gap and avoid having a performance gap in the inference rate.

But it's not just about resolution and bandwidth density. Packaging faces a combined problem having to deliver high yields at a larger and growing area for the package sizes. This is also driving this need to go into panel level processing and still be compatible with these resolutions and yields. And we need a productivity increase to supply the growing number and total area of these packaging sizes. So we developed a new fabrication process to try and solve this problem and it's called localized electrochemical manufacturing. This is a completely new process that combines patterning and deposition into a single co-optimized process. And by combining those two methods together, we're able to bypass some of the manufacturing challenges the existing processes have.

So I'm just going to explain this with an example of actually our patented electrode. So we use something called a stamp electrode to combine the pattern on the electrode so that the deposition process is selective. So effectively how our method works is we load material into a stamp into this pattern. We then place these stamps onto a substrate with a small amount of electrolyte and during the deposition of this process, the material stays inside the dielectric features. And what this gives is independence and a greater level of control. And with this additional control, we're able to improve the resolution, improve the uniformity, and fabricate structures that are otherwise very difficult to make, giving packaging designers more design freedom and more performance.

Now, you can see this process in action with our most recent LED tool. And so here for the first time we're demonstrating wafer scale deposition with stamps have been placed on the substrate, electrolyte being placed in between the stamp and the substrate, deposition and then removal of the stamp to reveal the pattern below. And in this example you can see five micron test structures be fabricated in single process. Now what Sienna has to announce today is that not only have we done this on wafers but for the first time and now it's in Taiwan, we have been able to use this method to fabricate entire layers on wafers and the next step for us is going to be doing this on dawbage and then also panel size substrates as well.

This is a method that is intrinsically compatible with different substrates, does not need to be round. The process is essentially stamp based instead. We also have the resolution to be able to continue scaling the scale and density. So we've demonstrated one micron resolution. We have also demonstrated submicron resolution. We have patterning examples down to 50 nanometers. It's a deep submicron. We have a lot of headroom to continue pushing this.

And we've designed this process from day one to be a drop-in tool replacement. So this is a more efficient process with less steps. So the total number of tools in the fab space required to deliver not only the same capability but improved capability in terms of resolution performance is less and that existing lines can be upgraded with this tool.

And so what does this mean in terms of packaging performance? If we combine the high resolution deposition capability with large area and the improved productivity, this is the recipe to be able to continue to improve chip-to-chip electrical bandwidth improvement and the total on-package bandwidth a 10x above and beyond what the existing roadmap is. And if we look out to the 2030s looking at panel size devices with submicron connections with electrical connections or multiple layers between these chips, we are now looking at 10 to hundreds of petabytes per second of total bandwidth which is a direct proportional increase in inference speed and effectively cost.

So to summarize there are two dimensions that the industry is looking to progress in packaging. One is bandwidth density, one is area and the Sienna technology has been purpose built to pursue both of those at the same time. Thank you very much.

>> Hello everyone. Thank you for coming and it's great to be here in Taiwan. You know, I've been here for almost every week out of the last, every week, every month out of the last couple of years. So it's great to be here and see friends and colleagues and all of our partners. So I'll talk a little bit about what Lightmatter is doing and give you an introduction to the company at this point. We're a bit more than a 10-year-old startup. So I think of us as a late phase startup. We raised a little bit more than a billion dollars of capital to date. Our founding story came out of some of the academic institutions in the US, MIT, Berkeley, the University of Colorado, Boulder and we've worked very deeply with our partners across the ecosystem to build what's becoming a new generation of optical connectivity and electronic photonic integration at large scale, you know, semiconductor scale high volume manufacturing.

So we've got great financial investors. Playground here has been one of our earliest and most supportive financial investors and we spend a lot of time building our strategic partnerships through equity investments and collaborative development activities. So TSMC, let's start with the ones in Taiwan. TSMC, MediaTek, Alchip, WeWin, and we view this as solving a huge problem across the whole ecosystem stack and we've had to partner deeply with these companies to work on this. And we're focused on bringing this Aqua Connectivity straight into what we call AI GPU or AI accelerator kinds of integrations. And to do that, we've also

worked closely with our partners AMD, Nvidia, and Intel. So, I was at this event last year and said that we were establishing an office here in Taiwan, and we got that entity established. We're investing aggressively in establishing the office space. So, I've got pictures here of the office. This is our office down in Shinju, and the construction on that office just recently completed in the last couple of months. We'll be having a grand opening probably sometime early next year. So, I'll look forward to inviting a number of you to come visit us at that opening. And we're also ramping our team here in Taiwan. So, we've got about, let's say, 10 people here right now, and we're going to be growing that over the next one to two years to really work deeply with our manufacturing partners, our ecosystem partners, here throughout Taiwan.

Now, what are we doing? Well, the previous speakers actually touched on it multiple times, but one of the problems and the big bottlenecks happening in these large-scale AI systems is trying to scale the bandwidth and data movement between different components of a rack-scale AI system. So today, the core AI network that connects these AI accelerators or GPUs together, it's bound to a single rack. And the reason it's bound to a single rack is because all of them are connected together electrically. So there are copper wires, copper cables that connect these GPUs and accelerators together. And that's where one of the biggest bottlenecks comes in, in trying to scale the number of GPUs and accelerators connected together. Now, why do you want to scale the number of GPUs and accelerators? Well, the short story is that if you can spread the AI workload across a larger number of nodes, you can scale system computation and system memory more elegantly with how the workload is running. So the AI workload that sits on top of this, its economics and its performance ends up depending on how you can connect all these different pieces together in a system. Now, electrically connected, you're bound to a single rack. What we want to do, if we want to bring this new generation of high-performance, densely integrated, co-packaged electronic and photonic solutions, so that we can break that electrical bottleneck and transition from the electrical connections that you see today into the optical connections that we want to go in the next couple of years and drive this improvement in rack-scale performance. So rather than being bound by a single rack, you can spread the AI workload across many racks and scale that connectivity gracefully.

So I mentioned this already, but and Pat did a great job setting the stage. You know, we view ourselves as helping bring an innovative new chiplet-scale technology into high-volume semiconductor manufacturing. And to do that, Taiwan is the center of the universe in terms of how you start to manufacture and deliver these things at scale. And this is just a few of our partners who we work with here in Taiwan very closely. Everything from the ASIC design partners, Alchip, MediaTek, GUC, of course, anchored by TSMC's role and position in this ecosystem. We also work closely with the OSATs who are forming the back end of the TSMC wafer fab, and all the way out to someone like Wiwynn, who's a strategic investor in our labs because we do the thought experiment all the way out to the chassis and rack-scale infrastructure and solve problems across this entire stack to really get things integrated in a high-volume, manufacturable way.

We had a great demo at Computex. I think probably some people came by earlier this year at that demo where we showcased more detail on what we're doing with our partner Wiwynn and the chassis designs and all the components and supply chain partnerships and ecosystems that are going into that. And also announced that we're joining UALink Consortium to help bring this innovation into a number of different fabric solutions so that we can really break this copper wall.

A bit of a zoom-in of what that looks like. We have some of this hardware over here at our table if you want to stop by and see it later. But this is what the chassis looks like. We want to integrate optically connected GPUs, accelerators, processors, as well as you can imagine this connected into memory and so-called scale-up switches, where that high-performance AI network is really scaling the connectivity of the core of the AI system.

So, thank you for your time. I'm glad to be here again and looking forward to visiting with all of you over here at our table. Thank you.

Thank you, Mark. A wonderful presentation. Thank you. And please return to your seat.

Please join me in welcoming the founder of PowerLattice to the stage. Thank you.

Good to be here. PowerLattice came from downstairs last year, same event. So it has been a tremendous year for us. So today I'm kind of introducing what we are doing and what's coming next.

So at PowerLattice we're really focusing on the last stage of the power path from data center, you know, power grid to the last stage, really the stage powering the GPU compute and also feeding thousands of amps of power into a single SoC. So we highlight here is all these today's components, right? All these point-of-load voltage regulator modules, all the working components surrounding the GPU. So that's really actually it's a really critical... so it is basically today's power delivery. So what's the problem of today? As computer power increase, single chip from 700 watts to 3,000 W, the overhead to deliver our power to the GPU, CPU actually more than what's computed. So you can see just only 5x increase of compute power, we actually require 20 times increase of the power overhead that's actually lost in our stage of power.

So what's the problem about this power delivery? Basically it is too big, too slow and sitting far away. To fundamentally solve this problem, so we have to really integrate the last stage of power delivery into silicon. So what we do in our lab is we actually build this monolithic point-of-load chiplet. We integrate everything in a single silicon. So we have a controller circuits, FETs and also integrated inductors.

So I would like to highlight the height of this single silicon is only 260 micrometers. So that kind of a small form factor really enables this chip to be integrated inside GPU package and very close to the compute.

So what we achieve here? So with this monolithic point-of-load chiplet we can deliver 200 times faster voltage regulation and speed and more than 400x power density.

So I'd like to show this in place. This is the first time we will showcase the impact of power delivery, the chiplets in the package to power the realistic workload. So this is the first time I'll show you.

So to summarize, the monolithic point-of-load is a reality. PowerLattice is doing that in the field and in the lab, and we believe for the future the point-of-load has to be monolithic. And we believe all that is the chiplet solution where it will become the de facto power point-of-load solution for power AI. Thank you.

Thank you. Very wonderful presentation. Thank you, and please return to your seat.

Please join me in welcoming the founder and CEO of Miko to the stage. Please give him a round of applause.

It's always fun to be back in Taiwan. So Pat mentioned that his first trip to Taiwan I think was 40 years ago. My first trip to Taiwan was 65 years ago when my mom brought me, or actually more accurately when my mom birthed me in Taiwan. So it's always good to be back. I always feel like it's coming home. And so, you know, Playground has been an excellent partner as we build up kind of PicoL and optical connectivity. You've heard from so many of their portfolio companies and it's just an exciting time both in Silicon Valley, of course, where we're all from, but also for the ecosystem in Taiwan. So I'll talk a little bit more about that today.

All right. So let me back up a little bit. Connectivity. You hear it all the time. But what's happening is for a hundred years or so, we had person-to-person communication. So think of those of us who were old enough, we used to actually have telephones on the wall and we would, you know, answer, etc. And then that moved to cell phones probably about 30 years ago. So those person-to-person calls were always limited by the voice and human being interaction, which is quite slow as far as the airway. And then about 30 years ago when the internet came, the person began to talk to the chip, right? It's memory, computers were looking for where to eat, right? Last night we went to Din Tai Fung, I had to find out how to get there, how to get Uber, that's a person-to-Uber type of communication. So that's still quite slow, right? Because if a millisecond delay happens, I don't notice that. What's changed in the last five years fundamentally is now we're talking all about chip-to-chip communication and that's changed everything, right? VCSELs have been around for 30 years, we've connected all the data centers that are more person-to-chip, but now chip-to-chip with hyperscale AI really is sensitive to bit errors, really sensitive to latency, and as Pat pointed out, power is also very, very sensitive as we build these very large hyperscale systems. So what are we doing about that and what are all these portfolio companies been talking about today? Is one of the things, two years ago when we started PicoL, I was invited to many talks around the world and one of the reasons was everybody thought VCSELs were over, right? 100G was the limit, VCSELs are dead, the future is something else, right? So I had to go and travel the world and be the VCSEL evangelist, etc. But something happened during that time, about six months ago, everybody came back to VCSELs, right? So a lot of people asked me what do you think about Coherent and Lumentum, Marvell, Credo, everyone talking about micro-VCSELs all of a sudden. And my answer to that is I love it, right? I can save my mileage, I don't have to travel the world talking about VCSELs, they're promoting it everywhere and now we can basically start working every day to make it a reality.

So we're working very closely with Win Semiconductor and TSMC, which is a partner of ours for over 10 years and we've been building billions. If you have an iPhone in your pocket, you probably have one of our VCSELs inside for Face ID. And so with that technology, we're getting ready to ramp micro-VCSELs. PicoL has already demonstrated 200G. At 50G for us, it's much easier. The problem isn't the speed for the VCSEL now. It's changed the packaging, right? So now you have much more channels when we talk about slow and wide. So that's really where the difficulty and where the advancement needs to happen.

All right. So while you're doing all this, power is really key, right? So we're trying to remove things like digital signal processing chips which take power, latency, all the things I mentioned, even the SerDes, right? The serializer-deserializer electrical signals within a chip are running at 32 Gbits, 50 Gbits. But in order to save the number of IO channels coming out, they want to slow that down. And I mean, I'm sorry, they want to aggregate that up to 200G, 400G in order to reduce the number of lanes necessary. But what that does is cause very, very high bandwidth requirements. At 200G, 400G, the noise, the signal, everything has to be cleaned up at the other end. So DSPs, digital signal processing chips are required, more power, etc. But by slowing it down, if I start talking slower, you're going to understand it better. And the same thing is for chip-to-chip. When we slow down the data rate, all the chips understand each other much better. Right? So now I don't need someone to kind of clean up the noise in between. I can get rid of the DSP. All that power goes away. So that's why this slow and wide movement is beginning to happen. Mainly driven because of power.

All right. So let me move through. So we basically are leveraging 30 years of VCSEL packaging here in Taiwan. Multiple partners we're working with, many of them unannounced. So you'll hear about them in the near future. But we are working very closely with Win right now to build the VCSEL. We've demonstrated the near-package optics pluggable. We've done 50G NRZ all produced already. Also 100G we're doing. And then we recently announced back in June the 200G VCSEL as well. So we can do all the different flavors from slow and wide up to 64, all the 100G that's shipping today in active optical cables. Then of course the fast and narrow at 200G coming in the next six months or so as well. So funny thing is when everybody moved to micro-VCSELs, they have this hexagonal plan and then one of the engineers in our team goes, 'Hey, our logo looks just like the hexagonal VCSEL that they're planning.' And so we believe that we're going to dominate the micro-VCSEL. We love the competition. We love that the larger companies are coming in and we believe that the future is micro-VCSELs. Thank you.

Thank you for the presentation. Thank you. Please return to your seat.

Please join me in welcoming Michael, CEO of Snowcap, to the stage. Thank you.

Thank you. So Snowcap, we are building hyperdense compute. The problem that exists today in electronics AI data centers, which you've heard over and over again today, is around the transistor, around the heat and the performance. As Peter has mentioned, over the past decade, we are not seeing increases in performance like we used to see because the power limitations, right? We've had these advances in line sizes and density, but we're not getting those improvements in power density from generation to generation.

So what that does is even though we reduce line sizes, we have to spread the transistors further apart in order to achieve the same power density at the chip level. So we can remove the heat. We keep packing the chips closer together. We keep, in order to do this, we keep increasing the cooling requirements of the systems, which means with the demand not only of more and more AI, but with the density within the racks themselves, we are generating these massive cooling systems and power requirements. As a result, just Meta alone, right? They've talked about their data centers and their hyperscale data center, for example, the size of, you know, Fifth Avenue in Manhattan, just a massive data center to keep up with their demands. And they of course propose data centers larger than that, more area than that. This obviously can't sustain. It has to be something that changes in order to make this a reality.

So at Snowcap, we have brought back a technology that was first demonstrated over 40 years ago: superconducting digital compute utilizing Josephson junctions instead of transistors to be the main carrier of energy in the system of compute. This technology has never made it to main scale because it's always been manufactured in lab environments and small capacity. We have brought this now to a 300 mm fab. We are producing this at scale at high density in advanced node manufacturing sites. The benefits of superconducting compute: the Josephson junction switch itself burns 100,000 times less power per toggle, which means taking advantage of that and zero loss in the superconducting wires inside of these systems means that we can pack these things very closely together. We don't need any passive components down inside of that system. This is a silicon interposer with superconducting wires with superconducting chips with hybrid bonding means less than 10 micron pitch interconnect. So all of the bandwidth problems that we always talk about in this AI space are solved by packing the chips very densely together at very low energy levels at massive amounts of bandwidth chip-to-chip from within the system. This is reducing an entire data center worth of compute into something the size of a suitcase.

So what we're demonstrating, what we are building is this data center scale compute inside of one small box. 100 times less power for the existing amount of compute. Or said the other way, I can take your existing data center and give you 100 times more compute inside the same data center with the same footprint, actually reduced footprint, and the same power budget that you already have. So no additional buildout required in order to switch to this technology.

As an example of what that means, in Arizona, Apple has a 480 exaflop data center facility. Utilizing our technology, with that, we can double its output. Simply four trucks in the parking lot, we can double the output of that entire facility. That massive reduction in compute scale. By reducing something from the size of a building to the size of a suitcase, we can drastically improve the amount of compute we get into the existing power infrastructure we already have in the world dedicated to AI data centers and computing in general. With that, thank you.

Thank you. Here it is. Whatever invite again, please return to your seat. Thank you.

Next, please join me in welcoming Pat Gelsinger, general partner at Playground Global, back to the stage for his closing remarks. Please give him a round. Thank you.